Barrier layers ferroelectric memory devices

Details Barrier layers ferroelectric memory devices Barrier layers ferroelectric memory devices

1999-10-20

2003-02-25

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S300000

Reexamination Certificate

active

06525357

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to barrier layers for semi-conductor devices, specifically to barrier layers for ferroelectric memory devices.
BACKGROUND OF THE INVENTION
Ferroelectric memories (FeRAM) combine advantages of both nonvolatile read only memory (ROM) and high speed random access memory (RAM). Two types of ferroelectric memory have been proposed in the prior art. One type, one transistor and one capacitor (
1
T-
1
C) memory, has a structure similar to that of the conventional dynamic random access memory. Such prior art memories are described, for example, in U.S. Pat. No. 5,767,541 to Hanagasaki, incorporated herein by reference. Fabrication of the
1
T-
1
C ferroelectric memory is relatively easy because the ferroelectric capacitor stacks are separated from the complementary metal-oxide semiconductor (CMOS) transistor layers by a thick interlayer dielectric film. However, while the ferroelectric medium in the capacitor is separated from CMOS transistor layers, there remain several critical integration related issues affecting the reliability of FeRAM. The interaction of a ferroelectric, such as PbZr
1−x
Ti
x
O
3
(PZT), capacitor with intermetallic dielectrics (IMD) and damage to the ferroelectric capacitor stacks due to hydrogen attack during IMD and subsequent metal and plug deposition are the most serious problems in the manufacture of high density FeRAM. Therefore, an encapsulating barrier layer between the PZT capacitor and IMD layer with high insulating and low leakage characteristics is necessary. At present, several metal oxides, such as TiO
2
, have been tested for this application; however, their performance is not satisfactory for high density FeRAM.
Another type of ferroelectric memory is the one transistor (
1
T) field effect type. Such devices are described, for example, by U.S. Pat. No. 3,832,700 to Wu, et al, incorporated herein by reference. At present, there is no reliable fabrication process available for this type of ferroelectric memory. Such a process would involve direct deposition of a ferroelectric layer on a silicon substrate in order to create a metal-ferroelectric-semiconductor field effect transistor (MFS FET). However, fabrication of a MFS FET incorporating PZT is extremely difficult because of the interaction of the PZT layer with Si and the formation of a low dielectric constant SiO
2
layer between the PZT layer and the Si substrate. For example, diffusion of oxygen through the layers of the memory device to the silicon substrate may result in the formation of an SiO
2
layer between the substrate and the adjacent ferroelectric layer, disrupting electrical communication between the substrate and the PZT layer. Lead atoms may subsequently leach out of the ferroelectric layer into the newly formed glassy SiO
2
layer, disrupting the network of silica bonds in the SiO
2
layer and further altering the electrical performance of the transistor. Several attempts have been made to fabricate MFS FETs using various barrier layers such Si
3
N
4
, CeO
2
, and Y
2
O
3
; however, none of them have produced satisfactory and reproducible results.
SUMMARY OF THE INVENTION
In one aspect, the invention is a method of preventing detrimental chemical and electrical interaction between two materials, especially a ferroelectric material and an adjacent material in a multi-layered electrical device. The method comprises disposing an electrically insulating, thermally and chemically stable barrier layer between the ferroelectric material and the adjacent, non-ferroelectric material. In one embodiment, the barrier layer restricts current flow and oxygen diffusion between the ferroelectric material and the non-ferroelectric material. In addition, the barrier layer is not reactive with the non-ferroelectric material. In this embodiment, the device may include a ferroelectric transistor, and the non-ferroelectric layer may be a semiconductor substrate. In another embodiment, the device may include a ferroelectric capacitor, and the barrier layer may protect the capacitor from damage during formation of the non-ferroelectric layer. In either of these embodiments, the barrier layer may comprise a mixed transition metal oxide which may in turn comprise ZrTiO
4
or SrTiO
3
, and the ferroelectric material may comprise PbZr
1−x
Ti
x
O
3
, SrBi
2
Ta
2
O
9
, and BaSr
x
Ti
1−x
O
3
. The barrier layer should have a high dielectric constant, preferably at least 10, more preferably at least 20, and even more preferably at least 30.
In another aspect, this invention is a multi-layer electrical device comprising a ferroelectric and a non-ferroelectric material and an electrically insulating, thermally stable barrier layer disposed between them. The multi-layer electrical device may be produced according to the method described above.
To form a barrier layer according to this invention, a high dielectric constant barrier layer disposed between the ferroelectric layer and Si substrate is preferred. The barrier layer should also exhibit low leakage current, a high breakdown voltage, and a low diffusivity for oxygen and other atoms comprising the ferroelectric material. For both
1
T and
1
T-
1
C devices, the layer should also exhibit high thermal and chemical stability.


REFERENCES:
patent: 3832700 (1974-08-01), Wu et al.
patent: 5365094 (1994-11-01), Takasu
patent: 5572052 (1996-11-01), Kashihara et al.
patent: 5753945 (1998-05-01), Chivukula et al.
patent: 5767541 (1998-06-01), Hanagasaki
patent: 5877977 (1999-03-01), Essaian
patent: 5933316 (1999-08-01), Ramakrishnan et al.
patent: 5955755 (1999-09-01), Hirai et al.
patent: 0540993 (1993-05-01), None
patent: 11126878 (1999-05-01), None
Alexander, et al., “Dielectric Characterization of Sol-Gel Derived Sn Doped ZrTiO4Thin Films”, Integrated Ferroelectrics, 17:221-230 (1997).
Shin, et al., “An Optimized Process and Characterization of Pb(Zr,Ti)O3Ferroelectric Capacitor for 1T/1C Ferroelectric RAM,” Mat. Res. Soc. Symp. Proc., 493:281-286 (1998).

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