Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-01
2001-06-05
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S003000, C438S253000, C438S643000, C438S785000
Reexamination Certificate
active
06242299
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to ferroelectric memories and ferroelectric capacitors. More particularly, the present invention relates to the protection of ferroelectric capacitors and memories from damage incurred during processing.
Ferroelectric films are used as the storage element in non-volatile memory circuits. A quantity of charge is liberated when the film is poled by an externally applied electric field. The quantity of this “switched charge” is crucial when fabricating a robust, reliable integrated circuit ferroelectric memory. If the amount of switched charge is reduced below a threshold level, the data state corresponding to the liberated charge quantity cannot be reliably ascertained.
Ferroelectric films are typically manufactured from lead perovskite-based materials such as PZT (lead zirconate titanate). The desirable electrical performance characteristics of PZT can be damaged by exposure to hydrogen either during integrated circuit processing steps or during subsequent packaging steps. Hydrogen can be produced from the breakdown of excess water in oxide layers, or by outgassing of packaging materials, as well as from countless other sources found during integrated circuit processing and packaging.
One technique for minimizing hydrogen exposure is by using a perovskite-based passivation layer as a “getter” layer for absorbing hydrogen. One problem with perovskite-based passivation layers is that there may be an undesirable interaction between aluminum wiring layers and the passivation layer. Multiple layer passivation layers and non-perovskite passivation layers have also been used to try to minimize hydrogen exposure without causing an undesirable chemical reaction with the aluminum wiring layers. In general, all passivation layers serve to mainly protect the ferroelectric integrated circuit from exposure to hydrogen during packaging. Also, a passivation layer effective in stopping packaging-related hydrogen may cause additional damage to the ferroelectric layer by trapping moisture stored in integrated circuit oxide layers.
Another technique for minimizing hydrogen exposure is by using an “encapsulation layer” wherein the top electrode of the ferroelectric capacitor is covered completely with a PZT or other perovskite-based layer, or by some other layer capable of absorbing hydrogen. While the encapsulation technique is widely believed to be extremely effective in reducing the amount of hydrogen exposure to the ferroelectric film, it can be greatly compromised by the top electrode contact that is etched into the encapsulation layer to provide electrical access to the top electrode.
What is desired, therefore, is an easily manufacturable solution for minimizing hydrogen exposure and related loss of performance during both integrated circuit processing and packaging of an integrated circuit ferroelectric memory.
SUMMARY OF THE INVENTION
It is, therefore, a principal object of the present invention to provide an uninterrupted barrier layer to protect a ferroelectric capacitor from damage and degradation during subsequent wafer processing, assembly processing, and use conditions.
It is an advantage of the invention that it allows the use of a single barrier layer.
It is another advantage of the invention that it allows full recovery of the ferroelectric capacitor, which may be difficult with prior art techniques such as barrier passivation.
It is another advantage of the invention that it avoids the loss of barrier integrity resulting from contact cuts through the barrier layer, as is the case with prior art barriers formed directly on the capacitor stack.
It is still another advantage of the present invention that it allows the use of processing techniques that would otherwise be harmful to the performance of the integrated circuit ferroelectric capacitors such as hot aluminum reflow plug fill, MLM (multi-level metal), CVDW (chemical vapor deposition tungsten) plugs, as well as silicon nitride passivation and ILD (interlevel dielectric) processes.
According to the present invention a continuous barrier layer is formed after the local interconnect layer is formed between the top electrode of a ferroelectric capacitor and the source/drain contact of a memory cell transistor in an integrated circuit ferroelectric memory. After contact has been made to the top electrode of the ferroelectric capacitor, a thin dielectric layer is deposited that provides a hydrogen barrier to the ferroelectric capacitor. The continuous barrier layer allows direct contact to the capacitor eliminating the need to offset the contact from the capacitor stack.
The process flow of the present invention uses a subsequent interlevel dielectric layer as a hard mask when patterning contacts through the barrier layer. This allows the flexibility to use a variety of barriers that are non-reactive and not easily etched using standard contact oxide etches, including but not limited to silicon nitride, aluminum oxide, titanium oxide, PZT, PLZT, SBT, BST, or high density silicon dioxide.
The use of an interlevel oxide layer as a hard mask to etch the barrier layer has additional benefits beyond flexibility in the choice of barrier layer material. The oxide layer hard mask reduces formation of polymer residues in the contact that may be present with other etching techniques, thus improving the integrity of subsequent metal interconnect. The use of the oxide layer as a hard mask also results in the corners and thickest areas of the oxide layer being etched without significant thinning of the minimum coverage areas, thus improving step coverage and ease of deposition of subsequent interconnects.
The inclusion of a sole barrier layer after local interconnect formation results in more flexibility during post-local interconnect processing including the use of multilevel metal and silicon nitride passivation, fewer restrictions on assembly procedures including choice of package type and assembly materials, and a more reliable finished product. The process flow of the present invention includes a method for subsequent contact cuts through the barrier layer that allows the use of barrier layers that are not easily etched using standard oxide etches. Inclusion of the sole barrier layer according to the present invention provides a sufficient barrier to hydrogen so that a memory cell structure can be constructed with or without a separate barrier layer directly on top of the capacitor stack.
The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings.
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Bowers Charles
Burton Esq. Carol W.
Huynh Yennhu
Meza, Esq. Peter J.
Ramtron International Corporation
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