Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-11-01
2002-06-04
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S758000, C438S761000, C438S778000, C438S792000, C438S793000, C438S479000, C438S931000
Reexamination Certificate
active
06399489
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the manufacture of integrated circuits, and more specifically, to a method of formation of a barrier layer for dual damascene processes.
In conventional integrated circuit fabrication, circuit elements are formed by etching a pattern of gaps in a layer of metal such as aluminum. The gaps are then filled with a dielectric such as silicon dioxide. Copper is poised to take over as the main on-chip conductor for all types of integrated circuits due to its lower resistance as compared to conventional aluminum alloys. Unfortunately it is difficult to etch copper and therefore, damascene processes have developed for fabrication of copper-based integrated circuits. In damascene processes, dielectric layers are deposited to form an integrated stack and then etched to form gaps that are subsequently filled with copper.
HDP-CVD fluorine-doped silicon oxide, also known as fluorosilicate glass (FSG) is an attractive solution to replace conventional silicon dioxide as intermetal dielectrics for damascene structures. FSG can be deposited in a conventional HDP-CVD systems which have been widely used for undoped silicate glass (USG) and FSG dielectrics in Aluminum interconnects. FSG has a good process scheme in terms of reliability, stability and throughput. The electrical performance of integrated circuits can be significantly improved due to the lower dielectric constant of FSG (about 3.3-3.6 compared to about 4.1-4.3 for conventional silicon oxides). The lower dielectric constant reduces the capacitance between metal lines in the same layer and reduces cross talk across layers.
The dielectric layers that separate layers of copper in a damascene structure are often referred to as intermetal dielectric (IMD) layers. IMD layers typically include a barrier layer to prevent diffusion of copper into adjacent dielectric layers such as FSG. Some integrated stacks used in damascene processes also utilize a layer known as an etch stop or hardmask to provide for selective etching of the film. Silicon nitride (Si
x
N
y
) is commonly used as a barrier layer or etch stop in damascene applications, for example when forming vias between layers containing metal lines. Unfortunately, silicon nitride has a relatively high dielectric constant k≈7.0 to 7.5 compared to 4.0-4.2 for silicon oxide or 3.3-3.6 for FSG, k. Consequently a dielectric layer containing silicon nitride will have an undesirably high fringe capacitance.
Generally, the thicker the layer of silicon nitride, compared to the FSG thickness, the larger the overall dielectric constant for the integrated stack. The effective dielectric constant of an integrated stack depends on the thickness and dielectric constant of each layer comprising the integrated stack. The dielectric constant of the overall film can be reduced either by reducing the thickness of the barrier layer or by using a barrier layer material with a lower dielectric constant. Present deposition processes can deposit suitable Si
x
N
y
films as thin as a few hundred angstroms in thickness or more. Existing techniques generally cannot deposit thinner films while maintaining the desired uniformity and overall film quality. Silicon-carbon-hydrogen based low-k barrier layers have been developed such as BLOK™ (Barrier Low K). BLOK™ is a trademark of Applied Materials, Inc. of Santa Clara, Calif. Such low-k barrier layers are typically deposited by plasma enhanced chemical vapor deposition (PECVD) using trimethylsilane (TMS). BLOK deposited using TMS provides capping solutions suitable for numerous processes, however alternative applications are desirable to enhance process integration.
Therefore, a need exists in the art for an inexpensive method of depositing an integrated stack including a low dielectric constant barrier layer that can be readily integrated with dielectric layer deposition.
SUMMARY OF THE INVENTION
The disadvantages associated with the prior art are overcome by a method of depositing a film, such as a barrier layer, on a substrate using a gaseous mixture that includes a silicon containing gas, and a hydrocarbon gas. The method generally comprises providing the gaseous mixture to the chamber, generating a plasma from the gaseous mixture, and depositing a film onto the substrate using the plasma. Suitable hydrocarbon gases include alkanes having the general formula C
x
H
2x+2
. Suitable alkanes include methane CH
4
), ethane (C
2
H
6
), butane (C
3
H
8
), propane (C
4
H
10
), etc. Suitable silicon containing gases include silanes having the general formula Si
y
H
2y+2
. The gaseous mixture may optionally include a flow of argon (Ar) to promote gas dissociation. In a preferred embodiment, the plasma is a high-density plasma. Preferably, the gaseous mixture has a carbon:silicon ratio of greater than 1:1, more preferably, between about 3:1 and 8:1. The resulting film has a C:Si ratio ranging from 55:45 to 65:35. Embodiments of the method of the present invention can deposit integrated stacks having an overall dielectric constant of about 4.0 or less. Such a stack may include a barrier layer having a dielectric constant of 3.0 or less. Integrated stacks and barrier layers deposited according to the present invention may be used in intermetal dielectric layers for dual damascene structures.
The method of the present invention may be embodied in a computer readable storage medium having a computer-readable program embodied therein for directing operation of a substrate processing system. Such a system may include a process chamber; a plasma generation system; a substrate holder; and a gas delivery system configured to introduce gases into the process chamber. The computer-readable program includes instructions for operating the substrate processing system to form a film on a substrate disposed in the processing chamber in accordance with embodiments of the above method.
These and other embodiments of the present invention, as well as its advantages and features are described in more detail in conjunction with the text below and attached figures.
REFERENCES:
patent: 4555464 (1985-11-01), Kido et al.
patent: 4557946 (1985-12-01), Sacher et al.
patent: 4789648 (1988-12-01), Chow et al.
patent: 4798629 (1989-01-01), Wood et al.
patent: 4812325 (1989-03-01), Ishihara et al.
patent: 4828880 (1989-05-01), Jenkins et al.
patent: 4845054 (1989-07-01), Mitchener
patent: 4894352 (1990-01-01), Lane et al.
patent: 4900591 (1990-02-01), Bennett et al.
patent: 4973511 (1990-11-01), Farmer et al.
patent: 4981724 (1991-01-01), Hochberg et al.
patent: 5028566 (1991-07-01), Lagendijk
patent: 5040046 (1991-08-01), Chhabra et al.
patent: 5120680 (1992-06-01), Foo et al.
patent: 5124014 (1992-06-01), Foo et al.
patent: 5204141 (1993-04-01), Roberts et al.
patent: 5224441 (1993-07-01), Felts et al.
patent: 5246887 (1993-09-01), Yu
patent: 5250473 (1993-10-01), Smits
patent: 5279867 (1994-01-01), Friedt et al.
patent: 5314724 (1994-05-01), Tsukune et al.
patent: 5352493 (1994-10-01), Dorfman et al.
patent: 5362526 (1994-11-01), Wang et al.
patent: 5364666 (1994-11-01), Williams et al.
patent: 5465680 (1995-11-01), Loboda
patent: 5466431 (1995-11-01), Dorfman et al.
patent: 5468520 (1995-11-01), Williams et al.
patent: 5494712 (1996-02-01), Hu et al.
patent: 5508368 (1996-04-01), Knapp et al.
patent: 5554570 (1996-09-01), Maeda et al.
patent: 5563105 (1996-10-01), Dobuzinsky et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5593740 (1997-01-01), Ikeda
patent: 5598027 (1997-01-01), Matsuura
patent: 5616369 (1997-04-01), Williams et al.
patent: 5618619 (1997-04-01), Petrmichl et al.
patent: 5637351 (1997-06-01), O'Neal et al.
patent: 5638251 (1997-06-01), Goel et al.
patent: 5661093 (1997-08-01), Ravi et al.
patent: 5683940 (1997-11-01), Yahiro
patent: 5693563 (1997-12-01), Teong
patent: 5700720 (1997-12-01), Hashimoto
patent: 5703404 (1997-12-01), Matsuuro
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5750210 (1998-05-01), Schmidt et al.
patent: 5753564 (1998-05-01), Fukada
patent: 5789319 (1998-08-01), H
Cho Seon Mee
M'Saad Hichem
Tribula Dana
Applied Materials Inc.
Smith Matthew
Townsend and Townsend and Crew
Yevsikor Victor
LandOfFree
Barrier layer deposition using HDP-CVD does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Barrier layer deposition using HDP-CVD, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Barrier layer deposition using HDP-CVD will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2959392