Barrier layer configurations and methods for processing...

Details Barrier layer configurations and methods for processing... Barrier layer configurations and methods for processing...

2011-03-01

2011-03-01

Chu, Chris (Department: 2815)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S118000, C438S622000, C438S643000, C438S653000, C257SE21021, C257S751000, C257S758000, C257S759000

Reexamination Certificate

active

07897507

ABSTRACT:
A microelectronic topography includes a dielectric layer (DL) with a surface higher than an adjacent bulk metal feature (BMF) and further includes a barrier layer (BL) upon the BMF and extending higher than the DL. Another microelectronic topography includes a BL with a metal-oxide layer having a metal element concentration which is disproportionate relative to concentrations of the element within metal alloy layers on either side of the metal-oxide layer. A method includes forming a BL upon a BMF such that portions of a first DL adjacent to the BMF are exposed, selectively depositing a second DL upon the BL, cleaning the topography thereafter, and blanket depositing a third DL upon the cleaned topography. Another method includes polishing a microelectronic topography such that a metallization layer is coplanar with a DL and further includes spraying a deionized water based fluid upon the polished topography to remove debris from the DL.

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