Barrier formation using novel sputter deposition method with...

Details Barrier formation using novel sputter deposition method with... Barrier formation using novel sputter deposition method with...

2002-01-09

2004-05-25

Whitehead, Jr., Carl (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S682000, C438S685000

Reexamination Certificate

active

06740585

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the fabrication of semiconductor devices and to the apparatus and methods for deposition and annealing of materials on a semiconductor substrate.
2. Description of the Related Art
Recent improvements in circuitry of ultra-large scale integration (ULSI) on semiconductor substrates indicate that future generations of semiconductor devices will require sub-quarter micron multi-level metallization. The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die as features decrease below 0.13 &mgr;m in size.
ULSI circuits include metal oxide semiconductor (MOS) devices, such as complementary metal oxide semiconductor (CMOS) field effect transistors (FETs). The transistors can include semiconductor gates disposed between source and drain regions. In the formation of integrated circuit structures, and particularly in the formation of MOS devices using polysilicon gate electrodes, it has become the practice to provide a metal silicide layer over the polysilicon gate electrode, and over the source and drain regions of the silicon substrate, to facilitate lower resistance and improve device performance by electrically connecting the source and drain regions to metal interconnects.
One important processing technique currently used in CMOS processing technology is the Self-Aligned Silicidation (salicide) of refractory metals such as titanium and cobalt. In a salicide process using cobalt (Co), for example, the source and drain and polysilicon gate resistances are reduced by forming a high conductivity overlayer and the contact resistance is reduced by increasing the effective contact area of the source and drain with subsequently formed metal interconnects. Salicide processing technology seeks to exploit the principle that a refractory metal such as cobalt deposited on a patterned silicon substrate will selectively react with exposed silicon under specific processing conditions, and will not react with adjacent materials, such as silicon oxide material.
For example, a layer of cobalt is sputtered onto silicon, typically patterned on a substrate surface, and then subjected to a thermal annealing process to form cobalt silicide (CoSi). Unreacted cobalt, such as cobalt deposited outside the patterned silicon or on a protective layer of silicon oxide, can thereafter be selectively etched away. The selective reaction of cobalt silicide will result in maskless, self-aligned formation of a low-resistivity refractory metal silicide in source, drain, and polysilicon gate regions formed on the substrate surface and in interconnecting conductors of the semiconductor device. After the etch process, further processing of the substrate may occur, such as additional thermal annealing, which may be used to further reduce the sheet resistance of the silicide material and complete formation of cobalt silicide (CoSi
2
).
However, it has been difficult to integrate cobalt silicide processes into conventional manufacturing equipment. Current processing systems performing cobalt silicide processes require transfer of the substrate between separate chambers for the deposition and annealing process steps. Transfer between chambers may expose the substrate to contamination and potential oxidation of silicon or cobalt deposited on the substrate surface.
Oxide formation on the surface of the substrate can result in increasing the resistance of silicide layers as well reducing the reliability of the overall circuit. For example, oxidation of the deposited cobalt material may result in cobalt agglomeration and irregular growth of the silicide layer. The agglomeration and irregular growth of the cobalt layer may result in device malformation, such as source and drain electrodes having different thicknesses and surface areas. Additionally, excess cobalt silicide growth on substrate surface may form conductive paths between devices, which may result in short circuits and device failure.
One solution to limiting cobalt and silicon contamination has been to sputter a capping film of titanium and/or titanium nitride on the cobalt and silicon film prior to transferring the substrate between processing systems. The capping film is then removed after annealing the substrate and prior to further processing of the substrate. However, the addition of titanium and titanium nitride deposition and removal processes increases the number of processing steps required for silicide formation, thereby reducing process efficiency, increasing processing complexity, and reducing substrate through-put.
ULSI circuits also include the formation of interconnects or contacts between conductive layers, such as the cobalt silicide layer described above and a copper feature. Interconnects or contacts generally comprise a feature definition formed in a dielectric material, such as silicon oxide, a barrier layer deposited on the feature definition, and a metal layer fill or “plug” of the feature definition. Titanium and titanium nitride films have been used as barrier layer material for the metal layer, such as tungsten, and the films are generally deposited by a physical vapor deposition technique. However, deposition of titanium over silicon surfaces presents the problem of titanium silicide formation.
Titanium silicide has been observed to agglomerate, which detrimentally affects subsequently deposited materials. Also, titanium silicide exhibits a radical increase in sheet resistance as feature sizes decrease below 0.17 &mgr;m, which detrimentally affects the conductance of the feature being formed. Further, titanium silicide has an insufficient thermal stability during processing of the substrate at temperatures of about 400° C. or higher, which can result in interlayer diffusion and detrimentally affect device performance.
Additionally, titanium and titanium nitride PVD deposition often occur at extremely low processing pressures, i.e., less than 5×10
−3
Torr, compared with CVD deposition of materials such as tungsten, which may be deposited as high as about 300 Torr. This results in difficult integration of PVD and CVD processes in the same system. This has resulted in many manufactures using separate systems for the PVD titanium and titanium nitride deposition and the CVD tungsten deposition. The increase in the number of systems results in increased production costs, increased production times, and exposes the processed substrate to contamination when transferred between systems.
Therefore, there is a need for a method and apparatus for forming barrier layers and silicide materials on a substrate while reducing processing complexity and improving processing efficiency and throughput.
SUMMARY OF THE INVENTION
Embodiments of the invention described herein generally provide methods and apparatus for forming a metal barrier or a metal silicide layer using a deposition and/or annealing process. In one aspect, a system is provided for processing a substrate including a load lock chamber, an intermediate substrate transfer region comprising a first substrate transfer chamber and a second substrate transfer chamber, wherein the first substrate transfer chamber is operated at a first pressure and the second transfer chamber is operated at a second pressure less than the first pressure and the first transfer chamber is coupled to the load lock chamber and the second substrate transfer chamber is coupled to the first substrate transfer chamber, at least one physical vapor deposition (PVD) processing chamber coupled to the first substrate transfer chamber, at least one chemical vapor deposition (CVD) processing chamber coupled to the second substrate transfer chamber, and at least one annealing chamber coupled to the second

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