Barrier and electroplating seed layer

Details Barrier and electroplating seed layer Barrier and electroplating seed layer

1999-08-27

2002-07-02

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S625000, C438S627000, C438S648000, C438S678000

Reexamination Certificate

active

06413858

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates in general to a barrier/seed layer in an integrated circuit, over which metal can be directly electroplated, and methods of making the same. More particularly, the invention relates to an in situ formed metal nitride barrier layer and metal seed layer for electroplating copper within vias or trenches.
BACKGROUND OF THE INVENTION
When fabricating integrated circuits (IC), layers of insulating, conducting and semiconducting materials are deposited and patterned. Contact vias or openings are commonly formed in insulating materials known as interlevel dielectrics (ILDs). The vias are then filled with conductive material, thereby interconnecting electrical devices and wiring at various levels. Damascene processing similarly involves etching trenches in insulating layers in a desired pattern for a wiring layer. These trenches are then filled with conductive material to produce the integrated wires. Where contact vias, extending downwardly from the bottom of the trenches, are simultaneously filled, the process is known as dual damascene.
Conductive elements, such as gates, capacitors, contacts, runners and wiring layers, must each be electrically isolated from one another for proper IC operation. In addition to interlevel dielectrics surrounding contacts, care must be taken to avoid conductive diffusion and spiking, which can cause undesired shorts between devices and contacts. Protective barriers are often formed between via or trench walls and metals in a substrate assembly, to aid in confining deposited material within the via or trench walls. Barriers are thus useful for damascene and dual damascene interconnect applications, particularly for small, fast-diffusing elements such as copper. Barriers also have application over transistor active areas and other circuit elements from or to which dopants tend to migrate during high temperature processing.
Candidate materials for protective barriers should foremost exhibit effective diffusion barrier properties. Additionally, the materials should demonstrate good adhesion with adjacent materials (e.g., oxide via walls, metal fillers). For many applications, a barrier layer is positioned in a current flow path and so must be conductive. Typically, barriers have been formed of metal nitrides (MN
x
) such as titanium nitride (TiN) or tungsten nitride (WN), which are dense, amorphous and adequately conductive for lining contact vias and other conductive barrier applications.
These lined vias or trenches are then filled with metal by any of a variety of processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), forcefill, hot metal reflow, etc. These methods attempt to completely fill deep, narrow openings without forming voids or keyholes. More recently, processing advancements have enabled the employment of copper as an interconnect material, taking advantage of its low resistivity. Typically, copper is electroplated over the substrate surface in order assure adequate filling of deep vias or trenches.
It is difficult, however, to satisfactorily electroplate copper (Cu) directly over the metal nitride barriers. Although metal nitrides can be sufficiently conductive for circuit operation, where current flows through the thickness of the barrier layer, lateral conductivity across such layers is inconsistent. High sheet resistivity makes it difficult to maintain an equipotential surface. Accordingly, a seed layer of copper is typically first deposited over the barrier, such as by PVD, and the workpiece is then transferred to an electroplating bath to complete the deposition. The seed layer thus represents an additional processing step, adding significantly to process overhead.
Accordingly, there is a need for improved processes and materials for protective barriers in integrated circuits. Desirably, such processes should also be compatible with conventional fabrication techniques, and thereby easily integrated with existing technology.
SUMMARY OF THE INVENTION
In accordance with one aspect of the invention, a method is provided for fabricating an integrated circuit. The method includes loading a semiconductor workpiece into a chamber and providing a metal source and a supply of nitrogen source gas to the chamber. A conductive barrier layer is deposited on the workpiece within the chamber from the metal source and the nitrogen source gas. The supply of nitrogen source gas is reduced while depositing the barrier layer.
In accordance with another aspect of the invention, a method is provided for forming a conductive structure in an opening in a partially fabricated integrated circuit. The opening can be, for example, a contact via or a wiring trench. A metal target is sputtered in the presence of an amount of nitrogen source gas, thereby forming a metal nitride layer in the opening. The amount of nitrogen source gas is reduced during the process. After reducing the amount of nitrogen source gas the metal target is further sputtered to form a substantially metal layer over the metal nitride layer in the opening. A second metal is then electroplated onto the top surface of the metal layer.
In accordance with another aspect of the present invention a method is provided for forming a wiring element with a barrier/seed layer in an integrated circuit. The method includes depositing an initial metal nitride layer, having a first nitrogen content, into an opening in an interlevel dielectric. A second metal nitride layer is deposited directly onto the initial metal nitride layer and has a second nitrogen content lower than the first nitrogen content. A substantially metal seed layer is then deposited directly onto the second metal nitride layer, and copper directly electroplated onto the substantially metal seed layer.
In accordance with another aspect of the invention, a protective barrier is interposed between a highly conducting metallic element in an integrated circuit and an interlevel dielectric. The barrier includes a metallic nitride sub-layer. A nitrogen content in the metallic nitride is graded from a first concentration adjacent the interlevel dielectric to about zero adjacent the metallic element.
In accordance with another aspect of the invention, an integrated circuit includes a wiring structure within an opening of an insulating layer. The wiring structure includes a barrier portion, which in turn includes at least one metal nitride sub-layer. A metal sub-layer directly overlies the barrier portion and has the same metal as the metal nitride sub-layer. A copper layer directly overlies the at least one metal sub-layer.


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