Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-10
2001-01-30
Monin, Jr., Donald L. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S270000, C438S271000, C438S589000
Reexamination Certificate
active
06180441
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to three-dimensional transistors and transistors having complex topography, and more particularly to field effect transistors using trenches and bars to enhance effective width.
BACKGROUND OF THE INVENTION
In conventional planar integrated circuit fabrication technology, in order to increase the current capacity of a field effect transistor, one must expand the width of the channel region in a direction parallel to the gate to get increased parallel current flow between the source and the drain of the device. Enhancement of the current capacity of a transistor has therefore usually meant increased occupation of semiconductor chip “real estate.” A need continues to exist for transistors exhibiting enhanced current carrying capacity but which do not have enhanced expense in terms of the semiconductor chip area that they occupy.
SUMMARY OF THE INVENTION
The present invention provides a solution to this technical problem by making the channel region and the insulated gate controlling the conductance of the channel region nonplanar. According to a first aspect of the invention, a field effect transistor is formed at the face of a semiconductor layer which has at least two depressions formed in its surface, preferably elongated in a first direction, the depressions being laterally spaced apart in a second direction by an eminence, ridge or bar with a top surface. Sidewalls of the eminence extend from the top surface thereof to the bottoms of the depressions. A conductive gate is formed on portions of the top and the sidewalls of the eminence to be insulatively spaced therefrom and to extend in the second direction. A source of the field effect transistor is formed on one side of the gate to include a portion of the eminence, and a drain is formed on the other side of the insulated gate to include another portion of the eminence. A channel region of the semiconductor layer formed underneath the gate spaces the source from the drain.
In one embodiment, the semiconductor layer has a plurality of trenches formed in its surface which are elongated in the first direction and which extend in a linear array in the second direction. An insulated gate is formed to intersect each of the trenches and the ridges defined between the trenches. A source and a drain are implanted into the semiconductor layer as self-aligned to the insulated gate, such that both the source and the drain occupy respective portions of the trenches and the ridges of semiconductor layer in between. The channel region in between the source and the drain has a series of valleys or trenches and mesas or ridges in between the trenches, with each portion of the channel region being proximate to a portion of the insulated gate.
According to another embodiment of the invention, portions of a semiconductor layer inside of an active device region are removed to leave a plurality of spaced-apart bars that are elongated in the first direction and are spaced from each other in a second direction at an angle to the first direction. An insulated gate is formed across each of the bars and the valleys in between the bars to extend in the first direction. As before, a source and drain implant can be self-aligned to this insulated gate. After filling the topography with an insulating layer such as oxide, contacts may advantageously be made to the source and drain of the transistor at the end of each bar, such that contact will be made both through a bottom and a sidewall of the contact hole.
The present invention confers a technical advantage in that by either forming trenches in the semiconductor surface or by forming elevated bars thereon, the resultant channel region has an increased surface area for the close adjacency of the insulated gate. Instead of just have a relatively planar surface for the insulated gate to pass across, there are a series of sidewalls of semiconductor material connecting ridges and valleys thereof, and the insulated gate is formed adjacent to these sidewalls also. This increases the effective width of the channel region between the source and the drain and therefore the current carrying capacity of the device. Devices may be built having an effective width that is substantially greater than the actual width.
REFERENCES:
patent: 4835584 (1989-05-01), Lancaster
patent: 5134448 (1992-07-01), Johnsen et al.
patent: 5155562 (1992-10-01), Tsuchiya
patent: 5177572 (1993-01-01), Murakami
patent: 5262336 (1993-11-01), Pike et al.
patent: 5283201 (1994-02-01), Tsang et al.
patent: 5432107 (1995-07-01), Uno et al.
patent: 5648283 (1997-07-01), Tsang et al.
patent: 5721443 (1998-02-01), Wu
Buynoski Matthew S.
Fang Peng
Liu Yowjuang W.
Yue John T.
Advanced Micro Devices , Inc.
Foley & Lardner
Monin, Jr. Donald L.
Rao S. H.
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