Banked memory circuit

Details Banked memory circuit Banked memory circuit

1985-01-29

1986-07-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365230, 365222, 365200, G11C 1130

Patent

active

046010181

ABSTRACT:
A memory circuit for interconnection to a computer including several memory banks, each bank including memory for the storage of information for the total address space addressable by the data processor. The memory circuit further includes a bank selection circuit connected to the data processor for receiving data representing a selected one of the memory banks. The memory circuit further includes a memory access circuit that determines from the bank selection circuit which one of the memory banks has been selected and provides alternating access between the selected memory bank and a specific memory bank in accordance with a timing signal from the data processor. The specific data bank includes display information and is accessed by the data processor during each interval when information is being output to the display. The memory circuit further includes a memory refresh circuit to refresh the memory banks by refreshing a limited number of memory banks during successive refresh time intervals in accordance with control signals from the display circuitry.

REFERENCES:
patent: 4332008 (1982-05-01), Shima et al.
patent: 4333167 (1982-06-01), McElroy
patent: 4387423 (1983-06-01), King et al.

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