Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2003-02-28
2003-11-11
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S701000, C257S703000, C174S260000, C174S261000, C361S748000
Reexamination Certificate
active
06646349
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor packages, and more particularly, to a ball grid array (BGA) semiconductor package in which a plurality of solder balls act as input/output (I/O) ports for electrically connecting a semiconductor chip mounted in the semiconductor package to an external device.
BACKGROUND OF THE INVENTION
Semiconductor packages are advanced devices each of which is incorporated with at least a semiconductor chip on a chip carrier (such as substrate, lead frame, etc) and uses a plurality of conductive elements such as bonding wires or solder bumps (in a flip-chip structure) for electrically connecting the chip to the chip carrier. The chip and conductive elements are hermetically encapsulated by an encapsulant made of a resin material such as epoxy resin. Such a packaged chip can be electrically connected to an external device (such as printed circuit board, PCB) for subsequent operation via a plurality of input/output (I/O) ports on the chip carrier such as solder balls formed on the substrate, outer leads of the lead frame, etc.
In order to produce various semiconductor packages of different types and functions, semiconductor chips are normally made with multiple functions or in various grades; in other words, semiconductor packages can be divided into various grades for providing different functions or performances according to operation of different or certain functions of chips mounted in the semiconductor packages. The above mechanism can be accomplished by different arrangements of bonding wires; for example, a chip may proceed with a particular function with a particular set of bond pads on the chip being formed with bonding wires, and another function may be operated by connecting bonding wires to another set of bond pads on the chip, making package products classified in functions by different arrangements of bonding wires. However, a drawback of this method is that the bonding wires must be formed before performing a molding process for fabricating an encapsulant. As a result, it needs to predict product demand or types of package products with functions desired or required in the market and to pre-form corresponding arrangements of bonding wires for providing desirable functions for package products. This may easily bring about a problem that pre-formed products are not compliant with practical requirements and fail to be flexibly adjusted in response to variation of product demand in the market, whereby it may be short of products in demand but full of stocks of products that are out of date, thereby leading to significant waste of costs.
U.S. Pat. No. 6,054,767 discloses a substrate for a ball grid array (BGA) semiconductor package, characterized in that the substrate is formed with a plurality of conductive vias penetrating through the same and a plurality of conductive traces on at least a surface of the substrate, the conductive traces being electrically connected to a chip mounted on the substrate. The conductive traces are situated between adjacent conductive vias or in proximity to the conductive vias, and selectively electrically coupled to the conductive vias by bonding wires to thereby control operation of desirable or certain functions of the chip. Therefore, functional classification of package products can be simply accomplished through the use of a single substrate, such that costs can be reduced and demanded products can be quickly commercialized and available in the market. However, this method still needs to be implemented before the molding process and thus renders the foregoing problems of waste of costs and failure in flexible adjustment in response to product demand change in the market.
U.S. Pat. No. 5,641,701 discloses the use of laser technology to cut off conductive traces and form disconnection. In particular, a package structure with a multi-functional chip is subject to a laser process to cut off or disconnect predetermined conductive traces that are electrically connected to the chip, so as to interrupt certain functions of the chip and thereby categorize package products. This method is beneficial that cutting of the conductive traces can be performed after the molding process, allowing package products with desirable or different functions to be timely fabricated and flexibly adjusted according to product demand in the market.
However, the above method in the use of laser technology would leads to significant drawbacks. One is preparation of a laser machine to perform the laser cutting process; this laser machine is expensively fabricated and thereby remarkably increases fabrication costs of package products. Moreover, laser-cutting of conductive traces easily causes contamination and requires an extra cleaning process that also increases fabrication costs. Further, laser power needs to be precisely controlled; due to delicate internal structure of a semiconductor package, other structural portions such as lower conductive traces underneath targeted conductive traces may be damaged by inaccurate power control of laser for cutting conductive traces, making production yield undesirably degraded. Accordingly, a solution is not to form any conductive trace underneath targeted conductive traces to be cut off, or to pre-form a copper layer underneath the targeted conductive traces, so as to prevent other or unintended conductive traces from being damaged by laser. However, this method restricts circuitry or routability on the substrate, which effect would be significantly severe for package products with conductive traces arranged in high density. Furthermore, conductive traces once being cut off cannot be electrically reconnected: that is, once a semiconductor package is adapted to proceed with particular functions, it fails to be subject to any more functional alteration, which is unfavorable in response to variation of product demand in the market.
Therefore, the problem to be solved herein is to provide a semiconductor package that can be formed with desirable functions by low costs and simplified fabrication processes for categorizing package products.
SUMMARY OF THE INVENTION
A primary objective of the present invention is to provide a ball grid array (BGA) semiconductor package, which utilizes solder balls to make conductive traces electrically conducted or disconnected, allowing the semiconductor package to be formed with predetermined or desirable functions.
Another objective of the invention is to provide a BGA semiconductor package in which fabrication costs and process complexity can be reduced.
A further objective of the invention is to provide a BGA semiconductor package, which can prevent structural damage and assure production yield.
In accordance of the foregoing and other objectives, the present invention proposes a BGA semiconductor package, comprising: a substrate having an upper surface and a lower surface opposed to the upper surface, the upper and lower surfaces being formed with a plurality of conductive traces each of which has a terminal, wherein an insulating material is applied over the upper and lower surfaces of the substrate to cover the conductive traces with the terminals of the conductive traces being exposed to outside of the insulating material, and a plurality of conductive vias are formed through the substrate for electrically interconnecting the conductive traces on the upper and lower surfaces, and wherein at least a predetermined position of the conductive trace is formed with a discontinuity, allowing the discontinuity and a portion of the conductive trace around the discontinuity to be exposed to outside of the insulating material and form a discontinuous pad; at least a chip mounted on and electrically connected to the upper surface of the substrate; an encapsulant formed on the upper surface of the substrate for encapsulating the chip; and at least a first solder ball selectively and detachably implanted on the discontinuous pad in a manner that, the conductive trace having the discontinuous pad is electrically conducted as the first solder ball
Huang Chien-Ping
Pu Han-Ping
Andujar Leonardo
Corless Peter F.
Edwards & Angell LLP
Flynn Nathan J.
Jensen Steven M.
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