Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2001-02-28
2002-09-10
Cuneo, Kamand (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S780000, C361S767000
Reexamination Certificate
active
06449169
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a BGA (Ball Grid Array) package with interdigitated power ring and ground ring.
2. Description of Related Art
BGA (Ball Grid Array) is an advanced type of semiconductor packaging technology which is characterized in the use of a substrate whose front side is mounted with a semiconductor chip and whose back side is mounted with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package can be mechanically bonded and electrically coupled to an external printed circuit board (PCB) by means of these solder balls.
Typically, the BGA substrate is formed with a power ring and a ground ring on the front side thereof The power ring is a ring-shaped electrically-conductive trace surrounding the packaged chip and is used to deliver the power from the external PCB to the packaged chip during operation, and the ground ring is a ring-shaped electrically-conductive trace arranged alongside the power ring and is used to connect the ground pads of the packaged chip to grounding lines on the external PCB.
FIGS. 1A-1B
show a typical BGA package with power ring and ground ring (note that
FIGS. 1A-1B
are simplified schematic diagrams showing only a small number of components; the actual BGA structure and circuit layout may be much more complex).
As shown, this BGA package includes: (a) a substrate
100
having A front side
100
a
and a back side
100
b
; (b) a ground ring
110
formed on the front side
100
a
of the substrate
100
; (c) a power ring
120
formed alongside the ground ring
110
; (d) a plurality of I/O pads
130
formed over the front side
100
a
of the substrate
100
; (d) a plurality of vias (electrically-conductive through-holes)
141
,
142
,
143
penetrating the substrate
100
, which include a subgroup of ground vias
141
each having an upper end connected to the ground ring
110
and a bottom end exposed on the back side
100
b
of the substrate
100
; a subgroup of power vias
142
each having an upper end connected to the power ring
120
and a bottom end exposed on the back side
100
b
of the substrate
100
; a subgroup of I/O vias
143
each having an upper end connected to one of the I/O pads
130
and a bottom end exposed on the back side
100
b
of the substrate
100
; (e) a solder mask
150
formed over the front side
100
a
of the substrate
100
while exposing the ground ring
110
, the power ring
120
, and the I/O pads
130
; (f) a semiconductor chip
160
having ground pads
161
, power pads
162
, and I/O pads
163
, and which is mounted on the front side
100
a
of the substrate
100
within the area surrounded by the ground ring
110
and the power ring
120
; (g) a set of bonding wires
170
, including a subset of ground wires
171
for connecting the chip's ground pads
161
to the ground ring
110
; a subset of power wires
172
for connecting the chip's power pads
162
to the power ring
120
; and a subset of I/O wires
173
for connecting the chip's I/O pads
163
to the substrate's I/O pads
130
; and (h) a ball grid array (an array of solder balls)
180
provided on the back side
100
b
of the substrate
100
, which includes a subgroup of ground balls
181
bonded to the ground vias
141
; a subgroup of power balls
182
bonded to the power vias
142
; and a subgroup of I/O balls
183
bonded to the I/O vias
143
. When this BGA package is mounted on an external PCB (not shown), it allows the ground balls
181
, the power balls
182
, and the I/O balls
183
to be coupled respectively to the PCB's V
CC
(system power), V
SS
(ground line) and I/O (signal input/output) lines.
Conventionally, the foregoing power/ground ring layout scheme on BGA package can be implemented in many various ways.
FIG. 2
is a schematic diagram showing a conventional power/ground ring layout scheme oh BGA package, which is disclosed in U.S. Pat. No. 5,686,699 entitled “SEMICONDUCTOR BOARD PROVIDING HIGH SIGNAL PIN UTILIZATION”.
As shown, this power/ground ring layout scheme includes the layout of a ground ring
110
′ and a power ring
120
′ surrounding the packaged chip
160
′, which are both shaped in straight lines and directly connected to ground vias
141
′ and power vias
142
′. Further, a plurality of ground wires
171
′ are connected from the chip's ground pads
161
′ to the ground ring
110
′, while a plurality of power wires
172
′ are connected from the chip's power pads
162
′ to the power ring
120
′.
One drawback to the forgoing power/ground ring layout scheme, however, is that since those points on the ground ring
110
′ and the power ring
120
′ that are already connected to the ground vias
141
′ and the power vias
142
′ are unbondable areas for the power/ground wires
171
′,
172
′, it would reduce the routability of the power/ground wires
171
′,
172
′. Therefore, the layout design for the power/ground wires
171
′,
172
′ would be difficult.
FIG. 3
shows a solution to the above-mentioned routability problem. As shown, this power/ground ring layout scheme includes the layout of a ground ring
110
″ and a power ring
120
″ surrounding the packaged chip
160
″, wherein the ground ring
110
″ is formed with a line portion
111
″ and a plurality of branched portions
112
″ extending out from the line portion
111
″ for connection to ground vias
141
″; and in a similar manner, the power ring
120
″ is formed with a line portion
121
″ and a plurality of branched portions
122
″ extending out from the line portion
111
″ for connection to power vias
142
″. This power/ground ring layout scheme allows the power/ground vias
141
″,
142
″ to be located beyond the line portions
111
″,
121
″ of the ground ring
110
″ and the power ring
120
″, thereby allowing power/ground wires
171
″,
172
″ to be straight routed to the nearest points on the line portions
111
″,
121
″ of the ground ring
110
″ and the powder ring
120
″. Therefore, the power/ground ring layout scheme shown in
FIG. 3
has a better routability than the prior art of
FIG. 2
, allowing the layout design work to be more convenient to implement.
The foregoing solution of
FIG. 3
, however, Us two drawbacks. First, since the provision of the branched portions
112
″,
122
″ of the ground ring
110
″ and the power ring
120
″ increases the length of the power/ground conductive path, it would undesirably degrade the electrical performance of the packaged/chip
160
″. Second, it would make the ground ring
110
″ and the power ring
120
″ farther separated from each other, which would additionally degrade the electrical performance of the packaged chip
160
″. Therefore, the power/ground ring layout scheme shown in
FIG. 3
would undesirably cause the packaged chip
160
″ to have poor electrical performance during operation.
FIG. 4A
shows a solution to the foregoing problem of degraded electrical performance, which is disclosed in the U.S. Pat. No. 5,726,860 entitled “METHOD AND APPARATUS TO REDUCE CAVITY SIZE AND THE BONDWIRE LENGTH IN THREE TIER PGA PACKAGE BY INTERDIGITATING THE VCC/VSS”.
As shown, this power/ground ring layout scheme includes the layout of a ground ring
110
′″ and a power ring
120
′″ surrounding the packaged chip
160
′″, wherein the ground ring
110
′″ is formed with a line portion
111
′″ and a plurality of toothed portions
112
′″, and in a similar manner, the power ring
120
′″ is formed with a line portion
121
′″ and a plurality of toothed portions
122
′″. To allow a reduced distance between the ground ring
110
′&Pr
Chen Chien-Te
Ho Tzong-Da
Liao Chih-Chin
Alcala Joseé H.
Corless Peter F.
Cuneo Kamand
Edwards & Angell, LLP.
Jensen Steven M.
LandOfFree
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