Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2000-03-27
2001-09-18
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S773000, C257S690000, C257S691000, C257S692000, C257S784000, C257S780000, C257S782000, C361S772000, C361S802000
Reexamination Certificate
active
06291898
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention generally relates to a ball grid array (BGA) package, and more particularly to a BGA package using a wire bonding technique.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the speed and the complexity of the IC chip have increased. Accordingly, a need has arisen for higher package efficiency. To meet the need, the ball grid array (BGA) technology has been developed by the semiconductor industry.
Although the conductive traces pads on a BGA substrate can be lithographically defined to achieve a very fine pitch, the bond pad pitch on the semiconductor die is typically restricted from achieving a comparable pitch due to spacing and design rules used to account for wire bonding methods and tolerances, such as capillary tool interference during wire bonding.
Conventional IC bond pad designs include (a) single in-line bond pad design and (b) staggered bond pad design. Typically, the number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require a substantial number of I/O connections. For high I/O count IC chips, the staggered bond pad design has been used so as to increase the maximum allowable pad number that can be designed on a chip. This has the benefit of providing not only more bonding pads per chip, but also shorter metal wires and thus faster circuits.
FIG. 1
shows a conventional plastic BGA package
100
comprising a chip
110
with a staggered bond pad design disposed on the upper surface of a substrate
120
. The chip
110
and a portion of the upper surface of the substrate
120
are encapsulated in a package body
150
. The upper surface of the substrate
120
is provided with a ground ring
122
, a power ring
124
, and a plurality of conductive traces
126
(see FIG.
2
). The active surface of the chip
110
is provided with a plurality of the bonding pads
112
positioned in two rows. The bonding pads
112
on the chip
110
typically include power pads, ground pads and I/O pads. The power pads are used for supplying the source voltage. The ground pads are used for supplying the ground potential.
Typically, the number of the I/O pads accounts for about two-thirds of the total number of the bonding pads
112
. Thus, at least some of the outer row of bonding pads
112
must be designed as I/O pads. The outer row of bonding pads
112
is referred to as bonding pads closest to the sides of the chip. Therefore, at least four tiers of bonding wires with different loop heights are required for avoiding short circuiting, wherein the bonding wires electrically connect the chip
110
to the substrate
120
. The first tier bonding wires
112
a
(lowest loop height) connect the ground pads designed in the outer row of the bonding pads to the ground ring
122
of the substrate
120
. The second tier bonding wires
112
b connect the power pads designed in the outer row of the bonding pads to the power ring
124
of the substrate
120
. The third tier bonding wires
112
c
connect the I/O pads designed in the outer row of the bonding pads to corresponding conductive traces
126
of the substrate
120
. The fourth tier bonding wires
112
d
connect the I/O pads designed in the inner row of the bonding pads to corresponding conductive traces
126
of the substrate
120
. The wire bonding parameters of each tier must be optimized separately. Therefore, the four tiers of bonding wires
112
a
,
112
b
,
112
c
,
112
d
require at least four times of wire bonding operations. Difficulty and risks of wire bonding are proportional to the number of wire bonding operations required.
It has been revealed that using an array of pads instead of using only perimeter pads can increase the maximum allowable pad number that can be designed on a chip. However, this will greatly increase the difficulty of wire bonding as described above.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide a BGA package which significantly increases the maximum allowable pad number that can be designed on a chip without increasing the tiers of bonding wires, thereby decreeing the difficulty of wire bonding.
The BGA package in accordance with the present invention comprises a chip with an array pad design disposed on the upper surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows: an inner row, a middle row, and an outer row along the sides of the chip. Only power supply pads and ground pads are designed in the outer row of bonding pads. All of the I/O pads are designed in the middle row of the bonding pads and the inner row of the bonding pads. The upper surface of the substrate is provided with a ground ring, a power ring, and a plurality of conductive traces.
Therefore, only three tiers of bonding wires with different loop height are required for avoiding short circuiting wherein the bonding wires electrically connect the chip to the substrate. The lower tier bonding wires connect the ground pads/power supply pads designed in the outer row of the bonding pads to the ground ring/power ring of the substrate. The middle tier bonding wires connect the I/O pads designed in the middle row of the bonding pads to corresponding conductive traces of the substrate. The upper tier bonding wires connect the I/O pads designed in the inner row of the bonding pads to corresponding conductive traces of the substrate. Therefore, the three tiers of bonding wires only require three separate wire bonding operations.
Accordingly, BGA package of the present invention can significantly increase the maximum allowable pad number that can be designed on a chip without increasing the tiers of bonding wires thereby decreasing the difficulty of wire bonding.
REFERENCES:
patent: 5468999 (1995-11-01), Lin et al.
patent: 5502278 (1996-03-01), Mabboux et al.
patent: 5962926 (1999-10-01), Torres et al.
patent: 6034427 (2000-03-01), Lan et al.
patent: 6037669 (2000-03-01), Shu et al.
patent: 405029546 (1993-02-01), None
Chao Te Tsung
Fang Hui Chin
Hung Ya Ping
Yeh Yung I
Advanced Semiconductor Engineering Inc.
Loke Steven
Parekh Nitin
Stevens Davis Miller & Mosher LLP
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