Ball grid array integrated circuit package structure

Details Ball grid array integrated circuit package structure Ball grid array integrated circuit package structure

2000-01-21

2002-03-19

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S700000, C257S782000

Reexamination Certificate

active

06359341

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit (IC) packages, and more particularly, to a BGA (Ball Grid Array) integrated circuit package having arrayed solder balls as I/O leads.
2. Description of Related Art
An integrated circuit package of the ball-grid-array (BGA) type is one that includes an array of electrically-conductive balls, such as solder balls, on the bottom side of the substrate for external connections of the integrated circuit package. The BGA package allows the integrated circuit package to be able to incorporate an increased number of I/O connections as compared to the conventional QFP (Quad Flat Package) devices. This benefit allows the BGA integrated circuit package to embed high-complexity and high-performance integrated circuits therein.
One problem arising from BGA integrated circuit packages having high-complexity and high-performance semiconductor chips, however, is that electrical noise would easily occur among the electronic components and electric circuits. The primary sources of such electrical noise are, for instance, switching noise which occurs on a current path arising from rapid current switching and crosstalk which occurs in a current path resulting from mutual capacitance and inductance between two adjacent current paths. Meanwhile, mutual inductance and self-inductance of conductive routes used for transmitting electrical signals between the semiconductor die and external electronic devices are also insignificant of electrical noise.
In addition, the electromagnetic radiations from the various electronic components in the integrated circuit package would cause undesired electromagnetic interference (EMI) to the nearby electronic devices, which would adversely affect the integrated circuit operation and electronic performance. Therefore, in the design and manufacture of integrated circuit packages, it is required to reduce the electromagnetic interference to minimum.
Conventionally integrated circuit packages are typically encapsulated in a resin-made encapsulate, and since resins are poor in thermal conductivity, the dissipation of the chip-produced heat during operation would be a problem. One solution is to provide a heat sink in the package. This practice, however, would increase the overall package weight and the complexity of the fabrication process, making the manufacture of the integrated circuit package quite laborious and cost-ineffective.
FIG. 5
is a schematic sectional diagram of a conventional BGA integrated circuit package disclosed in the U.S. Pat. No. 5,640,048, which is designed to solve the above-mentioned problems. As shown, this BGA integrated circuit package, as designated by the reference numeral
50
, includes a plurality of upper conductive traces
8
A,
8
B,
8
C,
8
C′ and lower conductive traces
10
A,
10
B,
10
C,
10
C′. The heat produced by the semiconductor chip
12
is conducted through a thermal path composed of the upper conductive traces
8
C, the vias
6
C, the ground plane
60
, the lower conductive traces
10
C, and the solder balls
14
C to the ground traces
20
C on the printed circuit board
18
. Since the distance between the ground plane
60
and the semiconductor chip
12
is less than the distance between the printed circuit board
18
and the semiconductor chip
12
, it also allows the ground plane
60
to dissipate part of the chip-produced heat during operation, thus allowing an increased heat-dissipation efficiency. In addition, since the ground plane
60
is located at a closer position to the semiconductor chip
12
than the printed circuit board
18
, it allows a reduced current return path, which can help reduce the mutual inductance between traces and hence the simultaneous switching noise. Moreover, the ground plane
60
also can help reduce the mutual coupling effect between the signal traces in the integrated circuit package, thus reducing crosstalk.
One drawback to the forgoing patent, however, is that electromagnetic interference is still a problem. Still one drawback is that the substrate of the BGA integrated circuit package is made by adhering a copper layer on the underside of a circuit board
52
having a core layer
56
sandwiched between symmetrically arranged copper layers, or alternatively on the aboveside of a circuit board
54
having a core layer
58
sandwiched between symmetrically arranged copper layers. This structure, however, cannot be manufactured by the currently-employed process for a two-layer BGA substrate, making the manufacture cost considerably high. Moreover, it is required to dimension the substrate to a thickness of up to the range from 0.02 inch to 0.03 inch (0.5 mm to 0.8 mm) for the purpose of providing sufficient rigidity to prevent the substrate from being bent and deformed during the mounting of the substrate on the circuit board. This substrate thickness, however, would make the overall package size unsatisfactorily large.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a BGA integrated circuit package, which has a better heat-dissipation efficiency and an improved electronic performance than the prior art.
It is another objective of this invention to provide a BGA integrated circuit package, which can help reduce electromagnetic interference which would otherwise interfere with external electronic devices.
It is still another objective of this invention to provide a BGA integrated circuit package, which can be manufactured utilizing the existent two-layer BGA substrate so as to make the manufacture more cost-effective than the prior art.
It is yet another objective of this invention to provide a BGA integrated circuit package, which has a reduced package size as compared to the prior art.
In accordance with the foregoing and other objectives, the invention proposes an improved BGA integrated circuit package. The BGA integrated circuit package of the invention comprises: (a) a semiconductor chip; (b) a substrate on which the semiconductor chip is mounted, which is composed of a core layer interposed between first conductive traces and second conductive traces, with the first conductive traces and second conductive traces being electrically connected to each other through a plurality of vias formed in the core layer; (c) a plurality of conductive balls electrically connected to the second conductive traces; (d) a ground metallic layer disposed over the first conductive traces, which defines a chip-receiving cavity for receiving the semiconductor chip therein; (e) a set of bonding wires for electrically coupling the semiconductor chip to the first conductive traces; and (f) an encapsulate which encapsulates the semiconductor chip, the bonding wires, the first conductive traces, and the ground metallic layer.
Since the ground metallic layer is made of a metal such as copper and formed around the semiconductor chip and located near the semiconductor chip and the first conductive traces, it can shorten the current return path, thereby reducing the inductance occurring between current paths and hence the simultaneous switching noise in the integrated circuit package. Moreover, it can help reduce the crosstalk between neighboring signal traces. Still more, since the ground metallic layer can act as a shield to electromagnetic radiation, it can reduce the electromagnetic interference. In addition, a portion of the surface of the ground metallic layer may be exposed to the outside of the encapsulate whereby the ground metallic layer provides the semiconductor chip with a direct heat-dissipation part to the ambient. As a result, the heat-dissipation efficiency of the BGA integrated circuit package of the invention is improved. These benefits make the BGA integrated circuit package of the invention more advantageous to use than the prior art of the U.S. Pat. No. 5,640,048.
The first conductive traces includes first power traces, first signal traces, first ground traces, and first thermal traces; and correspondingly, the second conductive traces include secon

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