Backside failure analysis capable integrated circuit packaging

Details Backside failure analysis capable integrated circuit packaging Backside failure analysis capable integrated circuit packaging

1998-08-28

2001-07-17

Bowers, Charles (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S106000, C438S127000, C438S126000, C257S676000

Reexamination Certificate

active

06261870

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to an integrated circuit package allowing easy access to the backside of the device for the purpose of failure analysis and, more particularly, to integrated circuit packages having an exposed backside or removable plug.
2. Description of Related Art
Integrated circuit packages are commonly inspected in order to detect defects in the manufacture of the package and, in particular, the encapsulated die. The process of analyzing defective packages to discover the cause of the defects is commonly referred to in the semiconductor industry as “failure analysis.” Advancements in the very large-scale integration (“VLSI”) processing related to higher integration and multiple level metalization schemes have greatly limited the ability to perform conventional failure analysis from the topside of the die. The semiconductor industry's response to this problem has been the development of backside failure analysis techniques. Backside emission microscopy is one of the most popular failure analysis techniques presently used in the semiconductor industry.
Examples of methods for removing silicon from the backside of semiconductor devices are disclosed in U.S. Pat. No. 5,252,842 (Buck et al.), U.S. Pat. No. 5,064,498 (Miller), U.S. Pat. No. and 4,784,721 (Holmen et al.). All backside techniques require that the package be opened using a combination of chemical and mechanical processes. In many cases the silicon must also be thinned after removing any packaging material. Because silicon, and especially doped silicon, is not perfectly transparent to near IR wave lengths of light, the silicon die must also be thinned. The most popular technique for opening IC packages involves the use of a mechanical grinder. Such systems are costly (about $50,000 to $70,000 each) and also expose the device to mechanical damage that could render the device unsuitable for electrical failure analysis. In fact, both mechanical and chemical etches are prone to cause damage to the die by chipping it or cracking it, thus leaving the device useless for most failure analysis procedures.
Accordingly, a need exists for an integrated circuit package that allows for easy access for backside failure analysis. The backside accessibility should ideally be accomplished at minimum cost and with the minimum potential for collateral damage to the package die.
SUMMARY OF THE INVENTION
A generic backside failure analysis capable integrated circuit package is provided in which the package is manufactured with an exposed backside or a removable plug. In the removable plug configuration, removal of the plug provides access for the purposes of backside failure analysis. Either configuration can utilize a standard or non-standard lead frame. When using a standard lead frame, the lead frame paddle is removed before the backside failure analysis begins. The non-standard package utilizes a lead frame which has been modified so that a majority of the die is not covered by the supporting paddle. Thus, it is not necessary to remove any portion of the paddle before conducting failure analysis. This invention allows easy access to the backside of a packaged device improving the failure analysis capabilities of the product.
The above as well as additional features and advantages of the present invention will become apparent in the following written detailed description.


REFERENCES:
patent: 4784721 (1988-11-01), Holmen et al.
patent: 5064498 (1991-11-01), Miller
patent: 5155068 (1992-10-01), Tada
patent: 5252842 (1993-10-01), Buck et al.
patent: 5351163 (1994-09-01), Dawson et al.
patent: 5604376 (1997-02-01), Hamburgen
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patent: 5698474 (1997-12-01), Hurley
patent: 5707485 (1998-01-01), Rolfson et al.
patent: 5990562 (1999-11-01), Vallett
patent: 6020748 (2000-02-01), Jeng

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