Background calibration of pipelined ADCs using flow control

Details Background calibration of pipelined ADCs using flow control Background calibration of pipelined ADCs using flow control

2006-08-01

2006-08-01

Mai, Lam T. (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000

Reexamination Certificate

active

07084804

ABSTRACT:
A modified pipeline architecture allows the simple implementation of a foreground calibration technique with the continuous calibration benefits of the background calibration techniques. To calibrate a stage in the pipeline, a calibration voltage is presented to the input instead of the output from the previous stage. To prevent loss of information, the output data of the previous stage is passed on to a stage further down.

REFERENCES:
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patent: 6340944 (2002-01-01), Chang et al.
J.M. Ingino and B.A. Wooley “A Continuously Calibrated 12-b, 10MS/s, 3.3-V A/D Converter”, IEEE Journal of Solid State Circuits, vol. 33, No. 12, Dec. 1998. pp. 1920-1931.
D. Fu, K. C. Dyer, S.H. Lewis and P.J. Hurst, “A Digital Background Calibration Technique fo Time-Interleaved Analog-to-Digital Converters”, IEEE Journal of Solid-State Circuits, vol. 33, No. 12, Dec. 1998. pp. 1904-1911.
U.-K. Moon and B.-S. Song, “Background Digital Calibration Techniques for Pipelined ADC's”, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, vol. 44, Feb. 1997, pp. 102-109.

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