Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
2001-12-06
2004-05-11
Clark, Sheila V. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S783000, C438S778000
Reexamination Certificate
active
06734532
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related in general to the field of electronic systems and semiconductor devices, and more specifically to materials and fabrication methods of back side coating of semiconductor wafers and the application in flip-chip assembly.
DESCRIPTION OF THE RELATED ART
The large majority of semiconductor devices are manufactured by attaching the passive surface of an integrated circuit (I/C) chip to a metallic leadframe, bonding the chip input/output (I/O) pads on the active surface to the leadframe leads with connecting wires, and encapsulating the assembly, including the sensitive wires, in molding compound. The leadframe for semiconductor devices and the transfer molding technique have been invented by U.S. Pat. No. 3,716,764, issued on Feb. 13, 1973 (Birchler et al., “Process for Encapsulating Electronic Components in Plastic”) and U.S. Pat. No. 4,043,027, issued on Aug. 23, 1977 (Birchler et al., “Process for Encapsulating Electronic Components in Plastic”).
On the other hand, semiconductor chips assembled “face-down” (active surface down) onto a substrate using solder balls, do not necessarily need a protective encapsulation, since there are no sensitive connecting wires to be protected. However, other reliability risks related to this “flip-chip” assembly as well as the requirements for special I/O pad metallizations, have been described in a series of detailed publications by the International Business Machines Corporation in 1969 (IBM J. Res. Develop., Vol. 13, pp. 226-296): P. A. Totta et al., SLT Device Metallurgy and its Monolithic Extension, L. F. Miller, Controlled Collapse Reflow Chip Joining, L. S. Goldmann, Geometric Optimization of Controlled Collapse Interconnections, K. C. Norris et al., Reliability of Controlled Collapse Interconnections, S. Oktay, Parametric Study of Temperature Profiles in Chips Joined by Controlled Collapse Techniques, B. S. Berry et al., Studies of the SLT Chip Terminal Metallurgy.
With the increasing demand to reduce the size and thickness of the semiconductor devices, current industry trend is to use the-bare silicon itself as the package. These “chip-size” packages (the extreme case of a “chip-scale” package) are usually bumped on the I/O pads to provide interconnections with the outside part (usually a printed circuit board). To keep the overall device thickness as low as possible, these devices are generally not molded or encapsulated in the traditional sense. However, in order to achieve some level of protection, liquid or viscous compounds have been applied to the exposed surfaces by screen printing or spinning. For these processes, specialized equipment and controls are needed to achieve sufficient product control, which, in turn, results in substantial equipment and process cost.
When unprotected devices are mounted on a printed circuit board (PCB) with the active chip surface down (flip-chip mounting), the bare passive chip surface of the device is exposed to the elements. Since semiconductor materials such as silicon are photo-sensitive, the exposure to ambient light of the passive chip surface can produce undesirable electrical noise, especially when the chip itself is thin.
An urgent need has, therefore, arisen for a coherent, low-cost method of protecting passive surface of the semiconductor chip from the ambient light. The challenge of cost reduction implies a drive for minimizing the number of process steps, and the application of standardized materials and process conditions wherever possible. The device structure should further enhance mechanical stability and high reliability. The fabrication method should be simple and suitable for batch processing, yet flexible enough for different semiconductor product families and a wide spectrum of design and process variations. Preferably, these innovations should be accomplished with minimum extension of product cycle time, and using installed equipment, so that no investment in new manufacturing machines is needed.
SUMMARY OF THE INVENTION
The present invention describes a semiconductor device comprising a semiconductor chip having an active and a passive surface; the active surface includes an integrated circuit (I/C) and input/output (I/O) pads suitable for metallurgical contacts. Further, the device has a protective plastic film of controlled and uniform thickness selectively attached to the passive surface. The film is suitable to absorb light of visible and ultraviolet wavelengths, to remain insensitive to moisture absorption, and to exert thermomechanical stress on the chip such that this stress at least partially neutralizes the stress exerted by an outside part after chip assembly.
The plastic film is selected from a group of electrically insulating materials consisting of polyimide, epoxy resin, and silicone, and the film further includes hardener, tackyfier, and fillers.
The film thickness preferably ranges from 20 to 60 &mgr;m, the light absorption is at least 96%, and the neutralizing stress is provided by a film coefficient of thermal expansion (CTE, about 18 to 45 ppm/° C.) approximately matching the CTE of the outside part, such as a printed wiring board. After curing the film has an adhesion strength of about 400 kg/cm
2
and a modulus of about 16 GPa.
The film is rolled onto the passive surface of the whole semiconductor wafer and cured at elevated temperatures, preferably about 150° C., for a length of time of about 1 hr. After film hardening, the wafer sawing process is applied to semiconductor and film material concurrently in order to singulate the individual chips.
The technical advances represented by the invention, as well as the aspects thereof, will become apparent from the following description of the preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims.
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patent: 6013953 (2000-01-01), Nishihara et al.
patent: 6023094 (2000-02-01), Kao et al.
patent: 6400037 (2002-06-01), Omizo
patent: 6582994 (2003-06-01), Jiang et al.
patent: 6650022 (2003-11-01), Qiet al.
Koduri Sreenivasan K.
Masumoto Kenji
Masumoto Mutsumi
Brady III Wade James
Clark Sheila V.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tung Yingsheng
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