Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2005-06-28
2005-06-28
Butler, Dennis M. (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000, C714S030000
Reexamination Certificate
active
06912665
ABSTRACT:
A test methodology is used to conduct an automatic chip timing analysis in coarse and fine resolution steps. Timing adjustment circuits implement coarse timing adjustment and fine timing adjustment for chip timing analysis. Timings such as clock, address and control inputs to a memory system can be digitally adjusted with respect to each other. A timer circuit is provided with a counter so that an incremental or decremental timing analysis can be carried out with a specific timing step. An algorithm is implemented which provides an effective, low-cost and accurate timing analysis. A nested loop is set up in the BIST where all possibilities of timing relationships between two or more signals can be applied to a device under test, and weaknesses, or failing timing conditions, can be found.
REFERENCES:
patent: 5396170 (1995-03-01), D'Souza et al.
patent: 5589788 (1996-12-01), Goto
patent: 6161420 (2000-12-01), Dilger et al.
patent: 6407641 (2002-06-01), Williams et al.
patent: 6714021 (2004-03-01), Williams
Ellis Wayne F.
Fifield John A.
Hsu Louis
Huott William V.
Butler Dennis M.
International Business Machines - Corporation
Walsh Robert A.
Whitham Curtis & Christofferson, P.C.
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