Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-03-10
2003-09-16
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S724000
Reexamination Certificate
active
06622272
ABSTRACT:
BACKGROUND OF THE INVENTION
In general, automatic test equipment (ATE) is equipment for testing electronic devices such as circuit boards or integrated circuits (ICs) in an automated manner. When an ATE system tests such a device (commonly referred to as the device under test or DUT), the ATE system typically applies stimuli such as electrical signals (e.g., voltages and/or currents) to the DUT and checks responses of the DUT. Typically, the end result of a test is either “pass” if the DUT successfully provides certain expected responses within pre-established tolerances, or “fail” if the DUT does not provide the expected responses within the pre-established tolerances. More sophisticated ATE systems are capable of evaluating a failed DUT to potentially determine one or more causes of a failure.
Some ATE systems can program and test bus-oriented components of a DUT. Programming DUT components customizes the DUT for its intended application. One such ATE system includes a controller, an input/output (I/O) interface, a tester and a bed of nails. Typically, the controller is a workstation or a personal computer (PC), and the tester is a channel card having multiple channels that enable the channel card to simultaneously provide and record multiple signals. The I/O interface typically connects the controller with the tester. Similarly, the bed of nails typically connects the tester with the DUT.
During operation, the controller sends numerous low level instructions and data to the tester through the I/O interface in order to configure the tester to program and test a specific bus-oriented component of the DUT. In particular, the controller provides signal generating data (e.g., signal sequences, voltage settings, voltage application time lengths, etc.), switch settings which control which portions of the bed of nails will be used during programming and testing, and test parameters such as those which define the length of the test and clock frequencies.
Once the controller has configured the tester through the I/O interface, the controller sends a special command to the tester, through the I/O interface, to begin programming and testing the specific bus-oriented DUT component. In response, channel circuitry within the tester generates signals having particular characteristics in accordance with the signal generating data. Furthermore, channel switches within the tester operate to route these signals to proper locations. As a result, the tester simulates one or more memory access cycles (e.g., FETCH, READ, WRITE, RESET, etc.) to program and test the bus-oriented DUT component.
Upon completion of the test, the tester provides recorded signal samples to the controller, through the I/O interface, for further processing (e.g., for a comparison with an expected response).
After the tester of the ATE system has completed testing of the bus-oriented component and has provided the results to the controller, the controller can reconfigure the tester to program and test another component of the DUT (e.g., another bus-oriented DUT component). To this end, the controller provides, through the I/O interface, new signal generating data, new switch settings and new test parameters which configure the tester to appropriately program and test the new DUT component. After testing of the new component is complete, the tester again sends the recorded signal samples to the controller, through the I/O interface, for further processing. The controller can repeat this process for other DUT components until the DUT is fully tested.
An ATE system which is similar to the above-described ATE system is described in U.S. Pat. No. 4,500,993 entitled “In-Circuit Tester for Testing Microprocessor Boards,” (Jacobson), the entire teachings of which are hereby incorporated by reference in their entirety. Another similar ATE system is described in Reissued U.S. Pat. No. RE 31,828 entitled “In-Circuit Digital Tester,” (Raymond et al.), the entire teachings of which are hereby incorporated by reference in their entirety.
SUMMARY OF THE INVENTION
In some conventional ATE systems a controller (i) configures a tester to program and test bus-oriented DUT components (as well as other DUT components), and (ii) receives recorded test results from the tester for further processing. In particular, for each component of the DUT to be tested, the controller typically provides numerous low level instructions and data such as signal generating data (e.g., voltage settings, voltage application time lengths, etc.), numerous switch settings, and test parameters to the tester through the I/O interface. Once the controller configures the tester using this information, the controller commands the tester to begin programming and testing that DUT component by sending a special command to the tester through the I/O interface. In response, the tester uses the instructions and data from the controller to properly generate signals and to properly operate the bed of nails which couples the tester to the DUT. At the end of each test, the tester typically returns recorded DUT component signal samples to the controller through the I/O interface for further processing.
Unfortunately, the data transfer rate between the controller and the tester, through the I/O interface, is often slower than the data transfer rate between the tester and the DUT, through the bed of nails. That is, more time is often required for the controller to configure the tester through the I/O interface, than for the tester to perform a programming and/or testing procedure on the DUT. Furthermore, upon completion of a test, additional time is required to transfer recorded test samples from the tester to the controller through the I/O interface for further processing. Such operation is essentially a bottleneck of the ATE system. That is, the numerous low level instructions and data passed between the controller and the tester for each DUT component test limits the overall throughput, i.e., programming and testing speed, of the ATE system.
In contrast to the above-described conventional ATE systems which require extensive use of the I/O interface to transfer numerous items of information (i.e., low level instructions, switch settings, sampled data, etc.) between the controller and the tester, the invention is directed to techniques for accessing an external device, e.g., programming and/or testing a DUT, using higher level memory access instructions between an ATE controller and an ATE interfacing apparatus, e.g., a specialized tester or channel card device. The use of such higher level instructions results in optimized communications between the ATE controller and ATE interfacing apparatus, and shorter overall programming and test times. Accordingly, the invention provides greater throughput over conventional ATE systems.
Furthermore, the use of higher level instructions enables ATE program and test developers to more easily develop ATE programming and testing procedures. For example, rather than require the developer to provide step-by-step details of the programming operation (i.e., numerous low level instructions), the developer can provide a few higher level instructions.
One arrangement of the invention is directed to an ATE system having a controller that provides a memory access instruction having a command and a test bus address; an interfacing apparatus (e.g., a specialized tester or channel card device) for accessing an external device (e.g., a DUT); and a test bus which connects the controller with the interfacing apparatus. The interfacing apparatus (i) receives the memory access instruction from the controller through the test bus, (ii) translates the test bus address into an identifier which identifies a portion of the external device, and (iii) accesses the identified portion of the external device based on the command and the identifier. Translation of the test bus address into the identifier, and accessing the external device based on the command of the instruction and the identifier alleviate the need for the ATE interfacing apparatus to receive numerous low le
Haverkamp Bernhard K.
Lim Lik Seng
Chapin & Huang , L.L.C.
Chung Phung M.
Huang, Esq. David E.
Teradyne, Inc.
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