Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-04-28
2000-12-26
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714736, G01R 3128
Patent
active
061675474
ABSTRACT:
An automatic self-testing system includes a plurality of sensor processing channels or paths each having a sensor for providing, either directly or indirectly, a digital value to a comparator which compares the measured value with predetermined value that is, in turn, provided to coincidence logic that evaluates the output of its comparator with the output of the comparators of the other paths to provide an output indicative of a pass/fail condition. Each sensor processing path includes two sub-paths that can be associated with or switched into the processing path while the disassociated sub-path undergoes off-line testing by a test processor. Testing is effected by providing a digital value to the sub-path under test while sensing the output to determine the functional validity of the sub-path under test. The combinational logic state of the system is monitored and converted into a decimal value that is compared with the set of decimal values corresponding to the finite known-good logic states of the system. The appearance of a decimal value that is not a member of the set of decimal values for the known-good logic states is thus an indication of a failure.
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Senechal Raymond R.
Wilkosz Stephen J.
Cady Albert De
CE Nuclear Power LLC
Crenshaw, Jr. Esq. Henry T.
Kananen Ronald P.
Lin Samuel
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