Automatic precharge apparatus of semiconductor memory device

Details Automatic precharge apparatus of semiconductor memory device Automatic precharge apparatus of semiconductor memory device

2001-01-02

2002-03-12

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S233100, C365S194000

Reexamination Certificate

active

06356494

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates in general to an automatic precharge apparatus of a semiconductor memory device.
2. General Background and Related Art
In a semiconductor memory automatic precharge arrangement according to conventional art, when a precharge command signal is input from an external source, a precharge operation is carried out, synchronized with the period of an external clock signal. When an internally generated precharge command signal is input, after writing/reading operations with a predetermined bust length in an internal circuit, a precharge operation is performed, synchronized with the period of an external clock signal.
When a semiconductor memory is driven by using a known auto precharge arrangement, which performs a precharge operation, synchronizing with the period of the external clock signal, the precharge arrangement controls so that in general, when a clock frequency is high, a precharge command signal is input from the outside after 2 to 3 clock periods and when a clock frequency is low, a precharge command signal is input after a predetermined period of time, such as, for example, 1 clock period.
However, in conventional precharge arrangements in which a precharge command signal is input, synchronized with the period of the external clock signal, there are several operational disadvantages. When the clock frequency of the external clock signal is high, a precharge command signal generated internally is input at high speed, and a high-speed precharge operation is performed. On the other hand, when the frequency of the clock signal is low, a precharge operation is performed after a longer period of time that is more than required to accomplish the desired result.
FIG. 1
is a timing diagram illustrating the operations of a conventional precharge arrangement that has the operational disadvantages mentioned above. After inputting a writing/reading signal Wt_RDb, a precharge operation is performed, synchronized with a clock signal CLK after a bust length (BL=the period of 4 clock pulses).
Since a precharge operation is performed, synchronized with a clock signal after inputting a writing/reading signal Wt_RDb and then a RAS signal is generated, there are operational disadvantages. When operating at a high frequency, a precharge operation is performed without fully securing a margin of an operation, thus there is a higher frequency of faulty operation. Conversely, during low frequency operationen, more clock pulses are used than necessary in an internal precharge operation so that the clocks hinder a high-speed operation.
SUMMARY
The claimed inventions feature, at least in part, a novel precharge arrangement for a semiconductor memory device. When an internal precharge command signal is input in writing/reading operations regardless of an external clock signal, a precharge operation is performed with a constant delay time after performing the last bust operation. It is controlled when an internal precharge command signal is input in writing/reading operations. A precharge operation is performed, synchronized with an external clock signal, after performing the last bust operation in the reading operation, and a precharge operation is performed after a constant delay time following by the last bust operation in the writing operation.
An exemplary embodiment of the automatic precharge apparatus of a semiconductor memory device includes an automatic precharge signal generating unit which receives external control signals and then generates an internal precharge command signal, and outputs an automatic precharge signal by using the internal precharge command signal and control signals related to a bust operation. A ras precharge signal generating unit receives the automatic precharge signal and then generates a ras precharge signal. A delay unit outputs a write recovery signal with a constant delay time, which is disabled in the reading operation and only enabled in the writing operation, when an internal precharge command signal is input in writing/reading operations. A ras generating unit generates a ras signal without a delay time when inputting an external precharge command signal, whereas after a constant delay time in response to the write recovery signal when inputting the ras precharge signal.
Thus, the claimed inventions feature an automatic precharge arrangement for a semiconductor memory device in which when a precharge command signal is input from an external source a precharge operation is performed without a delay time. However, when a precharge command signal is inputted from the inside, after writing/reading operations with a predetermined bust length in an internal circuit, a precharge operation is performed after a constant delay time regardless of the period of an external clock signal.


REFERENCES:
patent: 5014245 (1991-05-01), Muroka et al.
patent: 5608674 (1997-03-01), Yabe et al.
patent: 6104651 (2000-08-01), Cowles et al.

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