Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-31
2009-10-06
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07600208
ABSTRACT:
Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.
REFERENCES:
patent: 3619735 (1971-11-01), Chen et al.
patent: 5587333 (1996-12-01), Johansson et al.
patent: 6477694 (2002-11-01), Irino et al.
patent: 6523156 (2003-02-01), Cirit
patent: 6523159 (2003-02-01), Bernstein et al.
patent: 6532439 (2003-03-01), Anderson et al.
patent: 6550037 (2003-04-01), Ando et al.
patent: 6640331 (2003-10-01), Trivedi et al.
patent: 6671866 (2003-12-01), Arsintescu
patent: 6789241 (2004-09-01), Anderson et al.
patent: 6807656 (2004-10-01), Cao et al.
patent: 6898769 (2005-05-01), Nassif et al.
patent: 6937971 (2005-08-01), Smith et al.
patent: 7222320 (2007-05-01), Ogawa
patent: 7225418 (2007-05-01), Shimazaki et al.
patent: 7245516 (2007-07-01), Inoue
patent: 7269806 (2007-09-01), Berry et al.
patent: 7278120 (2007-10-01), Rahmat et al.
patent: 7302664 (2007-11-01), Haridass et al.
patent: 2003/0212538 (2003-11-01), Lin et al.
patent: 2003/0212973 (2003-11-01), Lin et al.
patent: 2006/0143585 (2006-06-01), Satoh et al.
patent: 2008/0098335 (2008-04-01), Allen et al.
patent: 2008/0134103 (2008-06-01), Zhao et al.
Chen et al., “On-chip decoupling capacitor optimization for high-performance VLSI design,” 1995 Proceedings of Int'l Symposium on VLSI Technology, Systems, and Applications, pp. 99-103.
Yan et al., “Floorplan-aware decoupling capacitance budgeting on equivalent circuit model,” 2006 IEEE, ISCAS 2006, pp. 1792-1795.
Su et al., “Optimal Decoupling Capacitor Sizing and Placement for Standard-cell Layout Designs,” IEEE Transactions on CAD of ICs and Systems, vol. 22, No. 4, Apr. 2003, pp. 428-436.
Chen et al., “On-chip decoupling capacitor optimization for noise and leakage reduction,” Proceedings of the 16thSymposium on ICs and Systems Design (SBCCI-'03), 2003 IEEE, 5 pages.
Zhao et al., “Decoupling capacitance allocation and its application to power-supply noise aware floorplanning,” IEEE Trans. on CAD of ICs and Systems, vol. 21, No. 1, Jan. 2002, pp. 81-92.
Pant et al., “On-chip decoupling capacitor optimization using architectural level prediction,” IEEE Trans. on VLSI Systems, vol. 10, No. 3, Jun. 2002, pp. 319-326.
Yeh et al., “Timing-aware power noise reduction in layout,” 2005 IEEE, pp. 626-633.
Na et al., “The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology,” 2004 Electronic Components and Technology Conference, pp. 556-567.
Scheffer, L. Lavagno, L. Martin, G; EDA for IC Implementation, Circuit Design, and Process Technology; 2006; pp. 20.1-20.14. Taylor and Francis Group, LLC. Boca Raton, FL, USA.
Bhushan Bharat
Kommoori Srivinas R.
Lee Albert
Parui Mithunjoy
Sharma Harsh Dev
Alford William E.
Alford Law Group, Inc.
Cadence Design Systems Inc.
Dang Sang
Garbowski Leigh Marie
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