Automatic output delay timing adjustment for programmable...

Details Automatic output delay timing adjustment for programmable... Automatic output delay timing adjustment for programmable...

2005-08-09

2005-08-09

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S401000

Reexamination Certificate

active

06928569

ABSTRACT:
A method for application in a data interface controller receiving asynchronous input data at predetermined one of a plurality of input bit frequencies, wherein the input data is sampled by the interface controller at a sample rate greater than the predetermined input bit rate, and wherein the sample rate is variable, and wherein the interface controller provides output data corresponding to the input data, but delayed by a delay amount that varies in accordance with the sample rate. The method is for providing a responsive signal event, responsive to a reference event in the delayed input data and at a predetermined time relative to an input bit time. In the method, a reference timing number is stored, representing the predetermined time in periods of the predetermined input bit frequency. An adjustment number corresponding to the delay amount is determined, in periods of the predetermined input bit frequency. The adjustment number is subtracted from the reference timing value to determine an adjusted timing number. A reference event is detected in the delayed input data, and in response thereto an adjusted timing number of periods of the predetermined input bit frequency is counted. A responsive signal event is provided at the time when the counting has ended.

REFERENCES:
patent: 5968180 (1999-10-01), Baco
patent: 6098888 (2000-08-01), Praden
patent: 6513719 (2003-02-01), Imura
patent: 6631481 (2003-10-01), Hoard et al.

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