Automatic generation and validation of memory test models

Details Automatic generation and validation of memory test models Automatic generation and validation of memory test models

2001-10-24

2004-11-02

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S189070

Reexamination Certificate

active

06813201

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to digital circuits, and specifically relates to memory testing.
BACKGROUND OF THE INVENTION
An application specific integrated circuit (ASIC) is a semiconductor chip that is produced for a customer using a design process substantially different from that used to produce custom semiconductor chips. ASICs can be designed using a suite of computer aided design (CAD) programs. Each ASIC is simulated to predict its performance under worst-case production tolerances. These simulations are used to ensure performance of the production chips. Simulations can be performed by carrying out experiments that utilize a digital computer representation of the system using data structures and programs.
For designing ASICs, several levels of modeling may be used. The levels are identified by the type of primitive components used. The primitive components of a particular model are those that cannot be structurally decomposed or divided into other recognizable components. Primitive components can be combined to form more complex components for a particular model. The primitives may be gates, or transistors, for example. In a transistor-level model, the primitives are transistors, and, at such a level, gates are functional (or high level) combinations of transistor primitives. On the other hand, at a gate-level description, the primitives are gates and the concept of transistors combined into gates does not apply.
For a typical ASIC design, three levels of modeling are utilized: the register transfer (RT)-level, the gate-level and the transistor-level. The RT-level provides a behavioral description of the design possibly including gate behavioral descriptions. The gate-level provides a Boolean representation of the design, as well as a representation of structural characteristics of the design. The transistor-level provides the most detailed electrical description of the design of the three levels and is used to ultimately create the layout of the ASIC.
The RT-level model is used to define the intended behavioral functioning of an ASIC design and the transistor-level model is used to create the manufacturing template or layout. ASIC design usually begins with an RT-level description. Once the intended functioning of the RT-level design is verified, its gate-level, and ultimately transistor-level, models are created through synthesis and technology mapping of the RT-level design.
For custom semiconductor chip designs, the RT-level and transistor-level models are developed separately, for most of the design, and are intended to model the same function. To verify that the RT-level and transistor-level models are equivalent, the transistor-level model is translated into a gate-level model through model abstraction and the RT-level is translated into another gate-level model through a synthesis process where the design is mapped into a technology library consisting of gate representations. The two gate-level models are then checked to ensure that they represent the same Boolean function by application of test patterns, or other methods. Because they are verified equivalent, the RT-level model is then used for simulation while the transistor-level model is used as a template to create the manufacturing layout.
Unfortunately, behavioral descriptions of embedded memories in an RT-level model cannot be efficiently (or correctly) synthesized into a gate-level model, nor can a transistor-level model of an embedded memory be processed using abstraction algorithms into a gate-level model. Consequently, transformations from the RT-level and the transistor-level description of embedded memories to the equivalent gate-level description must be done by hand. Such hand generation of the gate-level description is time-consuming, error-prone, and potentially costly. Furthermore, even if successfully generated, a gate-level embedded memory model is too complex for use as a memory test model. Test patterns can be created with an automatic test generation program (ATPG), by hand, or derived from functional programming code. ATPG uses the test models, including the memory test model, as the basis for generation of test patterns. The ATPG program can require its own set of primitives, typically for latches and memories among others.
FIG. 1
shows a schematic for memory model generation using a conventional technique. The example in
FIG. 1
relates to an integrated circuit such as, but not limited to, a microprocessor that includes an embedded memory, which requires a gate-level description. In the absence of an automated process, the gate-level description is created by hand. The microprocessor representation
100
includes a transistor-level design
100
A, an RT-level design
100
B, and a hand generated representation of the embedded memories
100
C, as described above. The microprocessor representation
100
yields a gate-level test model
102
, which can then lead to a test generation and fault simulation framework
104
. The process of generating test patterns for digital designs and validating their effectiveness is integrated in the design methodology. An automatic test pattern generation and fault simulation framework
104
, also referred to as a test framework, imports the gate-level test model
102
description of a design. In some instances, the RT-level design may be input into the gate-level test model
102
directly instead of the typical route using synthesis.
From a test perspective, that is using an ATPG program, an embedded memory can be understood with the transistor-level, RT-level or gate-level models. At one extreme, the detailed behavior of an embedded memory can be described so that within the test framework all the internal details of the memory are specified; at the other extreme, the memory could be treated as a module with unknown behavior, i.e., as an empty module. These memory test models are referred to as white box and black box test models, respectively. For the logic external to the memory, the non-memory logic, a gate-level representation of a design can be produced through synthesis or model abstraction. However, because synthesis and model abstraction is not efficient for embedded memories, the gate-level description of the memory itself is typically generated manually.
A white-box model of a memory, as described above, is a structure that includes, but is not limited to, all the components typical to a memory, such as a set of n×m memory cells, one or more write head(s), one or more sense amplifier(s) and possibly one or more address decoder(s); the components of a typical memory as listed form a structure which is referred to as a memory block. The boundary of the memory block in the RT-level model of a design is critical for implementing an automated memory test model generation process, and should match the boundary of the memory in the transistor-level model of the design. A memory is a structure that contains a memory block and possibly some random logic between the inputs and outputs (I/Os) of the memory block and any scannable storage elements or an I/O feeding such a scannable storage element. A memory array refers to the n×m array of memory cells in the memory block.
The memory block is modeled using either a structural or a memory primitive model. In the structural model, functions such as an address decoder, a write head and a sense amplifier are described in terms of random logic, which refers to combinational (e.g., AND or OR gates) and sequential (e.g., flops or latches) logic. Random logic excludes memory components such as random access memory (RAM). In this model, the memory cells are described in terms of flip-flops and latches. The structural model can be generated from a behavioral description of a memory model if the behavior of each component of the memory is described in sufficient detail. One of the drawbacks of the structural model is its large gate-level model size and complexity, which results in high test generation and fault simulation run times.
The memory-primitive model is an alternati

Affiliated with

Also associated with

Rating

Automatic generation and validation of memory test models does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic generation and validation of memory test models, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic generation and validation of memory test models will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3342117