Automatic erasing optimization circuit for an electrically erasa

Details Automatic erasing optimization circuit for an electrically erasa Automatic erasing optimization circuit for an electrically erasa

1990-12-31

1993-05-25

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Erase

36518909, 36523006, G11C 700

Patent

active

052146057

ABSTRACT:
There is provided an automatic erasing optimization circuit for an flash-type EEPROM including an erase sense means connected between the column decoder and the data input/output buffer for sensing the output state of the column decoder in response to a write enable signal and erasing signal to generate signals of opposite logics, a sequential output means consisting of a first, second and third resistors connected in series and receiving the output signals of the erasing sense means to respectively generate a first, second and third high voltage level control signals, a high voltage generating circuit for generating a high voltage equal to or greater than a given level to both the row decoder and the program latch circuit in response to pump clock pulses and the first, second and third high voltage level control signals, and an address counter for supplying the address buffer with address counting counting clock pulses in response to the output signal of the erasing sense means.

REFERENCES:
patent: 4408306 (1983-10-01), Kuo
patent: 4460982 (1984-07-01), Gee et al.
patent: 4648076 (1987-03-01), Schrenk
patent: 4888738 (1989-12-01), Wong et al.
patent: 4977543 (1990-12-01), Kouzi
patent: 5051953 (1991-09-01), Kitazawa et al.

Affiliated with

Also associated with

Rating

Automatic erasing optimization circuit for an electrically erasa does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Automatic erasing optimization circuit for an electrically erasa, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic erasing optimization circuit for an electrically erasa will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-903053