Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-07-05
2005-07-05
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06915497
ABSTRACT:
An automatic design system for designing wirings on circuit elements, includes an input device configured to receive circuit information, a glitch searching unit configured to search a glitch-occurring circuit element, a skew calculator configured to calculate a skew of a clock signal, a circuit information analyzer configured to define the calculated skew as a first target skew and determine whether the glitch can be reduced by setting the first target, a first target skew setting unit configured to set the first target, and a first latch insertion unit configured to insert a first latch.
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patent: 5648913 (1997-07-01), Bennett et al.
patent: 6272667 (2001-08-01), Minami et al.
patent: 6318911 (2001-11-01), Kitahara
patent: 6698006 (2004-02-01), Srinivasan et al.
Kitahara, et al., “A Clock-Gating Method for Low-Power LSI Design”,Proceedings Asia and South Pacific Design Automation Conference, pp. 307-312 (Feb. 1998).
Dinh Paul
Holmes Brenda O.
Kabushiki Kaisha Toshiba
Kilpatrick & Stockton LLP
Siek Vuthe
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