Automatic configuration of delay parameters in a dynamic...

Details Automatic configuration of delay parameters in a dynamic... Automatic configuration of delay parameters in a dynamic...

2001-01-25

2002-04-09

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C365S201000

Reexamination Certificate

active

06370067

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to dynamic memory controllers, and more particularly to a system for automatic selection of optimum delays for a dynamic memory controller.
DESCRIPTION OF RELATED ART
A typical system-on-a-chip system has a multi-function processor, a FLASH ROM device and a SDRAM device. The multi-function processor commonly includes a CPU core, a memory controller, and I/O modules. In addition to storing the boot image of the operating system, the FLASH ROM contains the delays required for proper setup of the memory controller interfacing with the SDRAM device. An SDRAM device is a type of RAM memory having two or more memory arrays that are interleaved in such a way that one array can be accessed while the other array prepares for access. The internal operations of an SDRAM device are synchronized to a clock signal provided by the memory controller. To permit the SDRAM to synchronize with the memory controller's system clock, a delay on the clock signal from the memory controller to the SDRAM and also a delay on the latching of the data signal returned from the SDRAM may be required. The delays may thus be denoted as transmit and receive delays, respectively. Typically, during the design of a system, an engineer manually finds the proper values for the transmit and receive delays, which are then burned into the FLASH ROM. This manual process is laborious and time-consuming, leading to the development of memory controllers that automatically adjust the delays to achieve proper timing. U.S. Pat. No. 6,137,734 discloses one such memory controller. It automatically searches through various combinations of transmit and receive delay pairs to determine whether successful memory read and write operations are achieved if the memory controller is configured according to each particular delay pair. The resulting collection of tested delay pairs, having either successful or failing results, may be arranged according to the delay values to form what is known in the art as a “shmoo” plot. A sample shmoo plot is shown in FIG.
1
. Note that selection of an optimal delay pair will avoid pairs adjacent to the edge of the shmoo plot. These delay pairs, although a memory controller configured according to them will communicate successfully with its SDPAM, are close enough to failing delay values that small changes in operating conditions could cause a memory controller choosing such an operating point to fail to synchronize with its SDRAM device. U.S. Pat. No. 6,137,734 discloses an algorithm to select an optimal delay pair. This algorithm, however may still pick operating points close to the edge of the shmoo plot. For example, consider the shmoo plot of FIG.
1
. The algorithm locates a line
5
parallel to the “x” axis (corresponding to the transmit delay) that includes the maximum number of passing points in the shmoo plot. Similarly, the algorithm selects a line
8
parallel to the “y” axis (corresponding to the receive delay) that includes the maximum number of passing points in the shmoo plot. The intersection
10
of these lines indicates the optimal selection according to this algorithm. However, for many shmoo shapes such as that shown in
FIG. 1
, this intersection may be located at the edge of the shmoo plot, far from the true optimal location
15
.
Thus, there is a need in the art for a dynamic memory controller that automatically adjusts its delay values using a robust algorithm to ensure the selection of an optimal delay pair.
SUMMARY
In accordance with one aspect of the invention, a method is provided of automatically selecting optimal delay pairs for configuring a memory controller according to the delay pair so it may communicate with a memory device. Various selected delay pairs are tested by the memory controller to determine whether communication with the memory device is successful. Delay pairs permitting successful communication are divided into a boundary set and a non-boundary set. The optimal delay pair is selected from the non-boundary set according to its relationship to the delay pairs in the boundary set.


REFERENCES:
patent: 6137734 (2000-10-01), Schoner et al.
patent: 6141265 (2000-10-01), Jeon

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