Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-12-21
2001-07-10
Heckler, Thomas M. (Department: 2182)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Reexamination Certificate
active
06260153
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates in general to an automatic compensation circuit for “no margin input data” and a clock capable of recognizing the input data normally, in the case that the clock and the data do not have any margin when reading the first data with a clock, and in case that data is inputted without any synchronized clock during designing Application Specific Integrated Circuit (ASIC) or Programmable Gate Array (PGA).
2. Background
Generally, a margin between a clock and input data is a time difference between the clock and the data edge. The margin between the clock and the data is required to read the input data exactly.
If input data has an incorrect location for synchronizing with a clock, and in particular has no margin with respect to the clock (hereinafter, referred to as “no margin input data”) when the input data is read, it is required to read the data after matching the data to the clock automatically.
Particularly, the margin between the data and the clock is quite important in an express data processing system (such as, DS-3), and it is required to synchronize the data having no connection with the margin.
When reading input data first for internal logic routing, like for a conventional PGA, a user should check the margin and determine phases between the input data and the clock with the oscillator. And in the case of no margin input data, the user reads the data with the positive or trailing edge where the margin exists.
But, whenever routing an internal logic circuit of a PGA, the circuit routing logic path is different. That is why it is difficult to read the data with the positive or trailing edge after determining the phase of the difference between the data and the clock which is changed.
SUMMARY
Accordingly, the present invention is provided to solve the problems. An object of the present invention is to provide an automatic compensation circuit for no margin data, capable of matching input data with a PGA internal clock, in which the data input to the PGA has an incorrect location for synchronizing with the clock, particularly has no margin with the clock after detecting the data.
One embodiment of the present invention to achieve the object provides an automatic compensation circuit for no margin input data, comprising no margin detecting means for detecting whether input data is input with no margin by checking whether the input data is detected to be overlapped on a system reading clock, and no margin compensating means for compensating for a lack of margin between the input data and the reading clock by selecting one of the no margin data and data having a proper margin according to a detected result of the no margin detecting means.
Another embodiment of the present invention to achieve the object provides an automatic compensation circuit for no margin input data, comprising no margin detecting means for detecting whether input data having no margin with respect to a system reading clock is input or not after checking overlapped data, input data reading means having different data transmission paths according to whether the margin between the input data and the reading clock exists or not, and no margin compensation means for compensating for a lack of margin between the reading clock and the input data by selecting one of the two reading paths automatically according to a detected result of the no margin detecting clock. Other technical advantages are readily apparent to one skilled in the art from the following figures, descriptions, and claims.
REFERENCES:
patent: 5517146 (1996-05-01), Yamasaki
patent: 5625506 (1997-04-01), Dovek et al.
patent: 5748231 (1998-05-01), Park et al.
patent: 6009534 (1999-12-01), Chiu et al.
Heckler Thomas M.
LG Information & Communications Ltd.
Long Aldridge & Norman LLP
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