Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-29
2002-12-10
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06493856
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an automatic circuit generation apparatus and method which automatically generate a circuit capable of eliminating a leakage current in a target circuit in a CMOS logical LSI, and relates to a computer program product for executing the automatic circuit generation method.
2. Description of the Related Art
Recently, according to miniaturizatlon of LSI layout design and lowering a supply voltage to the LSI, the threshold voltage Vth of a MOS transistor in the LSX is more decreased as low as possible. Because the lowering the threshold voltage Vth causes to increase the amount of a sub-threshold leakage current, the increasing of the sub-threshold leakage current in the MOS transistor also causes a serious problem to decrease the battery-life in battery drivers such as portable phones (or digital cellular phone), personal digital assistants, notebooks. palm-top computers, mobile communication terminals, and the like. The standby leakage current always flows through the MOS transistor on a standby mode (or a sleep period) and in an active mode in which the circuits comprising NOS transistors operate.
MTCMOS (MultiThreahold-Voltage CMOS) technology shown in
FIG. 1
has been proposed as a conventional method of reducing the leakage current. In this MTCMOS technology, the entire logical circuits (including a plurality of cells such as NAND cells and inverter cells In this example) is made up of MOS transistors of a low threshold voltage (L-Vth). In addition, logical circuits are connected to the virtual VDD line
61
and virtual VSS line
62
, and the virtual VDD line
61
and the virtual VSS line
62
are connected to a VDD line
65
and a VSS line
66
through KOS transistors
63
and
64
of a high threshold voltage (H-Vth), respectively. The voltages VDD mad VSS are supplied from external devices (not shown) to the VDD line
65
and the VSS line
66
. In order to reduce the amount of the leakage current, the MTCMOS method controls that both the MOS transistors
63
and
64
of the H-Vth are ON (the active mode) during the operation and both the MOS transistors
63
and
64
are OFF on the standby mode (the sleep period).
However, in the above-described conventional method based on the MTCMOS technology, the amount of the current to be supplied from the VDD line
65
to the virtual VDD line
61
and the amount of the current flows from the virtual VSS line
63
to the VSS line
66
during operation are determined according to the ON resistances of both the MOS transistors
63
and
64
of a high threshold voltage H-Vth. In order to achieve the high-speed operation of the LSI, it in necessary to reduce the ON resistance of each MOS transistor. That is, It is necessary to increase a width (W) of each of the KOS transistors
63
and
66
of the high threshold voltage H-Vth. This causes to increase the area of the LSI. Further, it must be necessary to determine the width of each MOS transistor of the high threshold voltage H-Vth based on following various conditions, for example:
First, the amount of the leakage current is greatly changed according to an input pattern supplied to a logical circuit: and
Second, in a case that a part of MOS transistors connected to the virtual VDD line
61
consumes a large amount of power, the level of a voltage on the virtual VDD line
61
is temporarily down. This decreased voltage affects the operation of other MOS transistors connected to the virtual VDD line
61
. For example, the operation speed of the MOS transistor is decreased. These problems described above lead to a complicated circuit design under MTCMOS technology.
Furthermore, there is VTCMOS (Variable Threshold-Voltage CMOS) technology shown in
FIG. 2
as a conventional leakage current decreasing technology. In VTCMOS, the entire logical circuit comprises low-threshold voltage MOS transistors
71
and
72
. A substrate voltage control (VT) circuit
73
supplies a substrate voltage (+&Dgr;V
1
and −&Dgr;V
2
) to both the MOS transistors
71
and
72
an the standby mode in order to enhance an effective threshold voltage Vth and to decrease the amount of the leakage current.
However, the use of this conventional VTCMOS technology requires to form a device with a triple-well structure in order to achieve the reliability of the device, and to form the device with the layout structure in which the substrate voltage is supplied to each MOS transistor independently. This demand also leads to a complicated circuit design under VTCMOS technology.
There is another conventional method of reducing the amount of the standby leakage current in which a power is shut down forcedly on the standby mode. However, in this conventional method, data items stored in memory circuits and flip-flops (F/F) mounted on a LSI are erased or broken. In order to avoid this drawback, although it must be necessary to create backup copies of required data items before the shutdown of the power, the system design becomes complicated. Furthermore, it is necessary to keep the time to restore the backup copies to the corresponding memory circuits and F/Fs when the standby mode is shifted to the operation mode in addition to the time to create the backup copies of the data items. This causes to increase the operation time period and to reduce the operation speed (performance).
The three conventional methods described above still have another serious problem, that is, the active leakage current during the active mode. According to progress of the miniaturization of LSI layout design, the power consumption of the active leakage current in the active mode becomes large, namely not negligibly when compared with that of the switching operation. Those conventional three methods cannot suppress the active leakage current that flows in the active mode.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional techniques, to provide an automatic circuit generation method and apparatus, and a computer program product for executing the automatic circuit generation method by a computer system. The automatic circuit generation apparatus and method of the present invention can automatically generate a circuit that reduces a standby leakage current during both the standby mode and active mode as low as possible with keeping a circuit performance such as operation speed and circuit area, in order to increase the efficiency of the circuit design.
According to an aspect of the present invention, an automatic circuit generation method and apparatus basically have a function defined by following steps (A) to (C): (A) Inputting circuit information, to be used for performing an automatic logical circuit generation, including a net list having high-threshold cells made up of only high-threshold voltage transistors, and interpreting the circuit information inputted; (B) Identifying a path whose delay time is larger than a timing constraint that has been set in advance by performing a static timing analysis for a logical circuit in the net list based on the result of the analysis for the circuit information inputted; and (C) Replacing high-threshold cells in at least a part of the path, whose delay time is larger than the timing constraint, with MT cells, each MT cell made up of the high-threshold voltage transistors and low-threshold voltage transistors.
REFERENCES:
patent: 5477475 (1995-12-01), Sample et al.
patent: 5774367 (1998-06-01), Reyes et al.
patent: 5903577 (1999-05-01), Teene
patent: 11-195973 (1999-07-01), None
Mutoh, S., et al. (1995) “1-V Power Supply High-Speed Digital Circuit Technology with Multithreshold-Voltage CMOS” IEEE J. Solid-State Circuits 30(8):847-854.
Kuroda, T., et al. (1996) “A 0.9-V, 150-MHz, 10-mW, 4 mm2,2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage(VT)Scheme” IEEE J. Solid-State Circuits 31(11):1770-1779.
Mutoh et al., IEEE Journal of Solid-State Circuits, “I-V Power Supply High -Speed Digital Circuit Technolo
Furusawa Toshiyuki
Kanazawa Masahiro
Kawabe Naoyuki
Koizumi Masayuki
Usami Kimiyoshi
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Lam Tuan T.
Luu An T.
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