Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate
2001-12-12
2003-02-25
Lam, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
With shift register
C365S189110, C365S078000
Reexamination Certificate
active
06525973
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to memory array testing, and more particularly to a system and method for quickly loading test patterns into a memory array.
BACKGROUND OF THE INVENTION
Many kinds of chips include memory on the chip. Prior to shipping these chips, this memory needs to be tested. Typically, each memory cell is programmed with a first data bit (e.g. a logic “1” value), then that data bit is read from the memory cell, then each memory cell is programmed with the opposite data bit (e.g. a logic “0” value), and then that data bit is read. In this way, the ability of each cell in the memory array to store logic “1” values and logic “0” values is verified.
There are several common test patterns that are typically used to test memory arrays. A test pattern is a particular sequence of logic “1” values and logic “0” values. For example, a checkerboard test pattern for an 8×8 memory array would have alternating logic “1” values and logic “0” values, for example, as shown in Table 1:
TABLE 1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
Conventionally, the data for this checkerboard pattern is programmed into a row of a memory array after being serially shifted into a bitline shift register. Memory arrays may be quite large, for example, 4096 rows and columns of memory cells supported by a 4096 latch bitline shift register. For a 4096 cell memory array, this conventional programming method requires 4096 data shifts to load the bitline shift register before each row of the memory array may be loaded. This lengthy delay in loading each row of a test pattern is repeated for each row of the memory array, adding undesirable delay in the memory testing process.
FIG. 1
is a block diagram of a conventional memory system
100
. Memory system
100
includes a four-latch bitline shift register
110
and a 4×3 cell memory array
120
. Bitline shift register
110
includes a bitline latch L
0
, a bitline latch L
1
, a bitline latch L
2
, and a bitline latch L
3
. Data QIN applied to bitline shift register
110
is serially shifted through bitline latches L
0
-L
3
. When bitline latches L
0
-L
3
store appropriate data, that data is stored in a row of memory array
120
. Memory array
120
includes three rows of memory cells, each row controlled by one of row lines RL
0
-RL
2
. Each row of memory cells includes four memory cells. For example, row
1
of memory array
120
, which is controlled by row line RL
1
, includes memory cells M
10
, M
11
, M
12
, and M
13
.
A checkerboard test pattern is conventionally applied to memory array
120
in the following manner. A logic “0” value is applied to bitline shift register
110
and shifted into bitline latch L
0
as data Q
0
. A logic “1” value is then applied to bitline shift register
110
. When the logic “1” value is shifted into bitline latch L
0
as data Q
0
, the former logic “0” value of data Q
0
is shifted into bitline latch L
1
as data Q
1
. Next, a logic “0” value is applied to bitline shift register
110
. When the logic “0” value is shifted into bitline latch L
0
as data Q
0
, the former logic “1” value of data Q
0
is shifted into bitline latch L
1
as data Q
1
and the former logic “0” value of data Q
1
is shifted into bitline latch L
2
as data Q
2
. Again, a logic “1” value is applied to bitline shift register
110
. When the logic “1” value is shifted into bitline latch L
0
as data Q
0
, the former logic “0” value of data Q
0
is shifted into bitline latch L
1
as data Q
1
, the former logic “1” value of data Q
1
is shifted into bitline latch L
2
as data Q
2
, and the former logic “0” value of data Q
2
is shifted into bitline latch L
3
as data Q
3
. As a result, bitline shift register
110
stores a data pattern of “1, 0, 1, 0”, as data Q
0
, Q
1
, Q
2
, and Q
3
. Row line RL
2
is enabled to write this data into memory cells M
20
, M
21
, M
22
, and M
23
, respectively.
As described above, four clock cycles are required to load four-latch bitline shift register
110
with a row of data for a checkerboard pattern prior to storing that data in a row of memory array
120
. Shift register
110
must then be loaded with the inverse pattern (e.g., a data pattern of “
0
,
1
,
0
,
1
” as data Q
0
, Q
1
, Q
2
, and Q
3
), taking another four clock cycles. This new data pattern is written into memory cells M
10
, M
11
, M
12
, and M
13
, respectively, by enabling row line RL
1
. Then the original pattern is re-loaded into bitline shift register
110
and store in memory cells M
00
, M
01
, M
02
, and M
03
. As a result, in addition to the clock cycles required to load each row of memory array
120
, twelve clock cycles are needed to load bitline shift register
110
. Considering a typical memory array of
4096
memory cells per row, the time required to load memory array
120
becomes a very time-consuming process.
It would be desirable to store rows of test pattern data in bitline shift register
110
in one shot to reduce the delays occurring during memory arrays testing.
SUMMARY
Accordingly, a system for testing a memory array is described that allows common memory test patterns to be loaded into a bitline shift register in one shot. In one embodiment of the present invention, a one-shot circuit including a pull-up transistor and a pull-down transistor is added to each bitline latch in the bitline shift register. The desired test pattern may be defined in software, which defines the pull-up and pull-down characteristics of the one-shot circuit for each bitline latch. During normal operation, the one-shot circuit does not affect the serial shifting of data through the bitline shift register. However, during loading of programmed memory test pattern data, the one-shot circuit allows all bitline latches within the bitline shift register to be loaded in parallel. This parallel loading of the bitline latches requires only one clock cycle, as opposed to N clock cycles for conventionally shifting a test pattern into an N-latch-wide conventional bitline shift register. For an N-row memory array, this time savings occurs for every row loaded with one-shot stored data. Consequently, the time required to load each row of the memory array is dramatically decreased.
The present invention will be more fully understood in view of the following description and drawings.
REFERENCES:
patent: 4388698 (1983-06-01), Allen
patent: 5282164 (1994-01-01), Kawana
patent: 5526390 (1996-06-01), Fucili
patent: 5742531 (1998-04-01), Freidin et al.
patent: 6137307 (2000-10-01), Iwanczuk et al.
Ahrens Michael G.
Shokouhi Farshid
Kubodera John
Lam David
Xilinx , Inc.
Young Edel M.
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