Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2003-11-19
2008-10-28
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S733000
Reexamination Certificate
active
07444564
ABSTRACT:
A bit fail map circuit accurately generates a bit fail map of an embedded memory such as a DRAM by utilizing a high speed multiplied clock generated from a low-speed Automated Test Equipment (ATE) tester. The circuit communicates between the ATE tester, the embedded memory under test, Built-In Self-Test (BIST) and Built-In Redundancy Analysis (BIRA). An accurate bit fail map of an embedded DRAM memory is provided by pausing the BIST test circuitry at a point when a fail is encountered, namely a mismatch between BIST expected data and the actual data read from the array, and then shifting the bit fail data off the chip using the low-speed ATE tester clock. Thereafter, the high-speed test is resumed from point of fail by again running the BIST using the high-speed internal clock, to provide at-speed bit Fail Maps.
REFERENCES:
patent: 4876685 (1989-10-01), Rich
patent: 5912901 (1999-06-01), Adams et al.
patent: 5936876 (1999-08-01), Sugasawara
patent: 5961653 (1999-10-01), Kalter et al.
patent: 6185709 (2001-02-01), Dreibelbis et al.
patent: 6255836 (2001-07-01), Schwarz et al.
patent: 6496947 (2002-12-01), Schwarz
patent: 6509766 (2003-01-01), Pomichter et al.
patent: 6643807 (2003-11-01), Heaslip et al.
patent: 6978402 (2005-12-01), Hirabayashi
patent: 2003/0084387 (2003-05-01), Rooney et al.
patent: 2005/0047229 (2005-03-01), Nadeau-Dostie et al.
patent: 7078495 (1995-03-01), None
patent: 2002243801 (2002-08-01), None
patent: 2002298598 (2002-10-01), None
patent: 2002-298598 (2002-11-01), None
International Test Conference, 1998 Proceedings, “Semiconductor Manufacturing Process Monitoring using Built-In Self-Test for Embedded Memories”, Ivo Schanstra, Dharmajaya Lukita, Ad J. van de Goor, Kees Veelenturf, Paul J. van Winjnen, pp. 872-881.
Anand Darren L.
Gorman Kevin W.
Nelms Michael R.
International Business Machines - Corporation
Kerveros James C
LeStrange, Esq. Michael J.
Scully , Scott, Murphy & Presser, P.C.
LandOfFree
Automatic bit fail mapping for embedded memories with clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Automatic bit fail mapping for embedded memories with clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Automatic bit fail mapping for embedded memories with clock... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4001904