Automatic ATAP test bench generator

Details Automatic ATAP test bench generator Automatic ATAP test bench generator

2006-04-04

2006-04-04

Thomson, W. (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S028000, C714S030000, C714S727000, C714S733000, C714S734000, C714S741000

Reexamination Certificate

active

07024346

ABSTRACT:
A system is provided for automatically generating ATAP test solutions. The system includes ATAP simulation circuitry, a bus, an ATAP test bench file, an output file, and a test program. The ATAP simulation circuitry is switchably coupled to a selected analog cell having an ATAP for applying analog tests. The bus is coupled with the ATAP simulation. The bus is operative to transmit and receive analog test simulation data. The ATAP test bench file is configured to receive the simulation data. The output file is operative to store the simulation data and deliver the simulation data to the ATAP simulation circuitry. The test program is generated by the ATAP simulation circuitry in the output file. The test program is configured to automatically generate ATAP test benches based upon chip-specific information. A method is also provided.

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Guo-Hun Zhu, Xuelong Yan, Ya Zhou and YueRen Guo, “The Algorithms of Inserting Boundary-Scan Circuit Automatically”, IEEE, 1998, pp. 527-531.
IEEE Standard for a Mixed-Signal Test Bus, IEEE Std 1149.4-1999, Published Mar. 28, 2000, pp. i-iii, 1-78.

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