Automatic adjusting method and circuit

Details Automatic adjusting method and circuit Automatic adjusting method and circuit

2005-09-27

2005-09-27

Cottingham, John R. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C345S088000

Reexamination Certificate

active

06950955

ABSTRACT:
When a communication speed of CPU104can be increased, a procedure of automatic phase adjustment involves setting phase shift amount CLK_DLY=n immediately after a vertical synchronization signal interrupt is generated, and reading video detection data VIDEO_DATA(n) after setting phase shift amount CLK_DLY=n+1 when the next vertical synchronization signal interrupt is generated. When CPU104is limited in the communication speed, the automatic adjustment is performed by an automatic adjusting circuit which has phase control data memory107, video detection data memory109, and a trigger input served by vertical synchronization signal S102.

REFERENCES:
patent: 5604513 (1997-02-01), Takahashi et al.
patent: 2003/0016199 (2003-01-01), Lee et al.
patent: 2004/0061675 (2004-04-01), Hirakawa et al.

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