Automated tests for built-in self test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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Details

C365S201000

Reexamination Certificate

active

11041608

ABSTRACT:
A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.

REFERENCES:
patent: 5901095 (1999-05-01), Crafts
patent: 6426904 (2002-07-01), Barth et al.
patent: 6681359 (2004-01-01), Au et al.
patent: 6728916 (2004-04-01), Chen et al.
patent: 7028240 (2006-04-01), Bautista et al.
patent: 2003/0223297 (2003-12-01), Fukuyama
patent: 1 388 788 (2004-02-01), None
International Search Report, Int'l Application No. PCT/US2006/002246, Int'l Filing Date Jan. 23, 2006, 3 pgs.

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