Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1997-09-24
1999-11-09
Nguyen, Hoa T.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
714727, 714729, G01R 3128
Patent
active
059833769
ABSTRACT:
In a control block design methodology, control block design proceeds without the inclusion of scan functionality until the functional design specifications are met. After meeting the functional design specifications, a scan insertion tool is executed to automatically insert scan functionality. The insertion is performed in such a manner that the functional cells within the control block are not perturbed. Therefore, functional timing may be minimally affected, if at all. In one embodiment, a scan enable buffer is inserted at the end of each row in the control block. Flops (or other scannable storage devices) within the row are connected to the scan enable line provided by the scan enable buffer within the row. Additionally, flops are connected into a scan chain on a row-by-row basis, minimizing the length of the wires connecting the scan chain. If a particular scan chain wire exceeds a length which will meet scan timing requirements, a scan chain buffer can be inserted as well (e.g. at the end of the row).
REFERENCES:
patent: 5717700 (1998-02-01), Crouch et al.
patent: 5859860 (1999-01-01), Whetsel
"IEEE Standard Test Access Port and Boundary-Scan Architecture," Published by the Institute of Electrical and Electronics Engineers Inc., New York, NY, Oct. 21, 1993, pp. 1-1-1-5.
Savir et al., "At-Speed Test is Not Necessarily an AC Test," 1991 IEEE, International Test Conference 1991, paper 26.3, pp. 722-727.
Varma, "On Path Delay Testing in a Standard Scan Environment," 199 IEEE, International Test Conference 1994, pp. 164-173.
Crouch et al., "Testability Features of the MC68060 Microprocessor," 1994 IEEE, International Test Conference 1994, pp. 60-69.
Li Hongyu
Lin Arthur
Narayanan Sridhar
Yu Yuncheng F.
Kivlin B. Noel
Merkel Lawrence J.
Nguyen Hoa T.
Sun Microsystems Inc.
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