Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1998-06-19
2000-11-21
Tu, Trinh L.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365201, G11C 2900, G11C 700
Patent
active
061516937
ABSTRACT:
An on-chip processor is used as a controller for burn-in and endurance testing of embedded non-volatile memory. An automated test machine downloads a test program into the non-volatile memory. The downloaded program contains a test program to be run on the non-volatile memory. When the burn-in or endurance test equipment activates the processor, the processor executes the program and performs a test on the non-volatile memory. The same method can be utilized to perform either the burn-in or endurance tests. Only the clock and reset lines are required to operate the test. Since the clock and reset lines are part of the processor's standard inputs, the method performs burn-in and endurance testing of an embedded non-volatile memory without bringing out the memory's address, data and control lines to the package pins of the integrated circuit. Since the clock and reset lines are part of the standard burn-in and endurance test equipment, the method also performs the testing without the use of expensive burn-in or endurance test equipment.
REFERENCES:
patent: 4873705 (1989-10-01), Johnson
patent: 5073891 (1991-12-01), Patel
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5675546 (1997-10-01), Leung
Arnold Robert H.
Bell Richard D.
Kohler Ross A.
McPartland Richard J.
Wheeler Paul K.
Lucent Technologies - Inc.
Tu Trinh L.
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