Automated fault diagnosis in a programmable device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C714S741000, C714S725000, C714S025000, C714S002000, C702S117000, C707S793000

Reexamination Certificate

active

10955560

ABSTRACT:
A method and apparatus are disclosed that simplify and reduce the time required for detecting faults in a programmable device such as a programmable logic device (PLD) by utilizing fault coverage information corresponding to a plurality of test patterns for the PLD to reduce the set of potential faults. For one embodiment, each test pattern is designated as either passing or failing, the faults that are detectable by at least two failing test patterns and the faults that are not detectable by any passing test patterns are eliminated, and the remaining faults are diagnosed. For another embodiment, the faults detectable by each failing test pattern are diagnosed to generate corresponding fault sets, and the faults not common to the fault sets and not detectable by one or more of the failing test patterns are eliminated.

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