Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-05-31
2004-03-09
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C327S163000, C709S241000
Reexamination Certificate
active
06704892
ABSTRACT:
BACKGROUND
This invention relates to testing processors.
Integrated circuit devices such as processors may be subjected to industry standard test protocols such as the IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Standard 1149.1 (1990) (hereinafter referred to as IEEE 1149). In IEEE 1149, a device which may be called a tester is coupled through a test access port (TAP) to an integrated circuit device under test. The device under test may include a plurality of cells that allow different components of the integrated circuit to be tested. Each of these cells may receive input information and may provide output information through a so-called scan procedure. Thus, the integrated circuit may be subjected to a number of test signals and the response of the integrated circuit may be scanned out and analyzed. In some cases, the integrated circuit may be caused to execute one cycle at a time so that the results of each cycle may be analyzed.
In normal operation, one or more phase locked loops (PLLs) may be utilized in a processor. The role of a PLL in a processor is to synthesize an internal chip clock as well as to account for any clock distribution skews. By accounting for clock distribution skews, the processor may operate synchronously.
In some high-speed processors, there is an input/output (I/O) PLL and a core PLL each producing a separate clock signal. Both PLLs share a common reference clock that is supplied externally. Each PLL also receives a signal from a feedback loop that includes its own clock distribution tree. Each clock distribution tree includes a plurality of state elements that receive and utilize the signal produced by a PLL. The feedback loop signals are utilized to enable each PLL to account for clock distribution tree skews.
In systems with two PLLs, the two resulting clock signals are aligned because of the use of a common reference clock together with feedback signals seen at the end of each clock distribution tree. Each PLL must generate a clock signal and account for skews so that all of the state elements in the clock distribution tree see the same clock signal at the same time both within the processor as well as in interfaces to external integrated circuits.
In one test mode, the PLL or PLLs of a processor may be bypassed. One may wish to bypass the PLLs to be able to debug the processor without the PLLs in the picture. One example of a situation where one may wish to do this is when it is desired to operate the processor in regions outside the PLL's specified range. One may want to test the processor outside the PLL's range in order to ensure that the processor works beyond the specified operating range. Other test modes, in addition to a PLL mode and a bypass mode may be utilized as well.
One may also want to bypass the PLLs to isolate PLL introduced errors from those errors introduced by the clock distribution tree. For example, a PLL mode and a bypass mode may be run side-by-side to examine errors, jitter or other clock inaccuracies that occur in one mode versus those that occur in another mode.
In some cases, the bypass mode may be more effective for debugging than in a mode in which the PLLs are utilized. For example, it may be desirable to run varying pulse lengths within a given cycle. It may be easier to do such analyses without using a PLL, especially in cases when multiple clock edges may be of importance.
In addition, because the PLLs are basically analog circuits that operate in digital integrated circuit, there may be cases when it is desirable to operate without the PLLs. The most apparent of these is the situation where the design of the PLL is not complete and yet it is still desired to test the logic circuits.
In modern processors which operate at very high frequencies and which use multiple PLLs, a number of problems arise in attempting to utilize a bypass mode. For example, without the PLLs there is no way to synthesize the clock signals in a space efficient way. Merely adding additional on-chip PLLs may take too much space. Moreover, in a bypass or test mode, using an auxiliary PLL may simply perpetuate the same types of errors that arose from the original PLL.
Another problem arises from the fact that the PLLs also compensate for clock distribution tree skews. If the PLLs are bypassed, it is desirable to avoid clock distribution skews.
Finally, in high speed processors, the resolution of the automated test equipment may become an issue. In order to achieve sufficiently high frequency signals from different signal edges and with different signal channels from the tester, the tester channel accuracy may become an issue. Tester channel accuracy arises from equipment accuracy, processor package routing skew and on-die signal skew. Thus, it is desirable for the edges and channels to all be aligned to avoid generating distorted clock signals that have different shapes, duty cycles or periods. Without the PLL, there is no way to account for these tester channel inaccuracy problems.
Thus, there is a need for a way to operate high speed processors in a PLL bypass mode.
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Barkatullah Javed S.
Frodsham Tim
Kurd Nasser A.
O'Brien David J.
De'cady Albert
Gandhi Dipakkumar
Intel Corporation
Trop Pruner & Hu P.C.
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