Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-10-03
2006-10-03
Chung, Phung My (Department: 2138)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S736000
Reexamination Certificate
active
07117415
ABSTRACT:
Methods and systems for reducing the volume of test data associated with built in self testing (BIST) test methodologies (e.g., logical BIST, array BIST, etc.) and pattern structures are provided. Embodiments of the present invention store a limited number of “dynamic” test parameters for each test sequence that have changed relative to a previous test sequence.
REFERENCES:
patent: 5951705 (1999-09-01), Arkin et al.
patent: 6282134 (2001-08-01), Kumar
patent: 6323639 (2001-11-01), Park
patent: 2002/0188902 (2002-12-01), Fan et al.
Forlenza Donato O.
Forlenza Orazio P.
Hurley William J.
Robbins Bryan J.
Chung Phung My
Patterson & Sheridan LLP
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