Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-06-21
2008-10-14
Louis-Jacques, Jacques (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S715000, C714S738000, C714S730000, C714S724000, C714S706000, C714S704000, C714S707000, C714S708000, C714S712000, C709S230000, C365S201000, C365S189050
Reexamination Certificate
active
07437643
ABSTRACT:
Training of a link is performed, wherein the link is an interconnect between two devices of a computer system. A built-in self-test (BIST) of the link is performed. A result from the link training is compared to a result from the BIST. A link status of the link is posted, wherein the link status is based at least in part on the result from the link training and the result from the BIST.
REFERENCES:
patent: 5974502 (1999-10-01), DeKoning et al.
patent: 6505317 (2003-01-01), Smith et al.
patent: 6684292 (2004-01-01), Piccirillo et al.
patent: 6826100 (2004-11-01), Ellis et al.
patent: 6907377 (2005-06-01), Slaight et al.
patent: 7132823 (2006-11-01), Ng et al.
patent: 7139957 (2006-11-01), Querbach et al.
patent: 2003/0046618 (2003-03-01), Collins
patent: 2004/0117707 (2004-06-01), Ellis et al.
patent: 2004/0117708 (2004-06-01), Ellis et al.
patent: 2004/0117709 (2004-06-01), Nejedlo et al.
patent: 2004/0186688 (2004-09-01), Nejedlo
patent: 2004/0193976 (2004-09-01), Slaight et al.
patent: 2004/0193986 (2004-09-01), Canagasaby et al.
patent: 2004/0204879 (2004-10-01), Slaight et al.
patent: 2004/0204912 (2004-10-01), Nejedlo et al.
patent: 2005/0021797 (2005-01-01), Talaat et al.
patent: 2005/0080581 (2005-04-01), Zimmerman et al.
patent: 2006/0149982 (2006-07-01), Vogt
patent: 2006/0150030 (2006-07-01), Mirabeau et al.
patent: 2006/0200713 (2006-09-01), Slobodnik et al.
patent: 2007/0022335 (2007-01-01), Shin et al.
Nejedlo, Jay J., “IBIST™ (Interconnect Built-in Self-Test) Architecture and Methodology for PCT Express: Intel's Next-Generation Test and Validation Methodology for Performance IO,” ITC International Test Conference, 2003 IEEE, pp. 114-122.
Khanna Rahul
Kumar Mohan J.
Nejedlo Jay
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Louis-Jacques Jacques
Merant Guerrier
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