Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2011-04-12
2011-04-12
Tu, Christine (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S733000, C714S734000
Reexamination Certificate
active
07925942
ABSTRACT:
An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
REFERENCES:
patent: 5570375 (1996-10-01), Tsai et al.
patent: 6058255 (2000-05-01), Jordan
patent: 7117413 (2006-10-01), Park et al.
patent: 7590910 (2009-09-01), Haroun et al.
Haroun Baher S.
Whetsel Lee D.
Bassuk Lawrence J.
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tu Christine
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