At-speed transition fault testing with low speed scan enable

Details At-speed transition fault testing with low speed scan enable At-speed transition fault testing with low speed scan enable

2006-04-25

2009-12-29

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000, C714S744000

Reexamination Certificate

active

07640475

ABSTRACT:
A method and/or a system of at-speed transition fault testing with low speed scan enable is disclosed. In one embodiment, a digital system includes any number of scan chains. Each scan chain may have any number of scan cells, an at-speed local scan enable signal to control a mode of operation, and any number of last transition generator cells. In addition, each last transition generator cell includes a first flip-flop with an output connected to a second flip-flop input, an input multiplexer to apply any one of a first flip-flop output data and an OR gate having a first flip-flop input based on a state of the at-speed local scan enable signal, and an OR gate having a first flip-flop output and the global scan enable signal as inputs to generate the at-speed local scan enable signal based on a state of the global scan enable signal.

REFERENCES:
patent: 5889788 (1999-03-01), Pressly et al.
patent: 6023778 (2000-02-01), Li
patent: 6567943 (2003-05-01), Barnhart et al.
patent: 6622273 (2003-09-01), Barnes
patent: 6671860 (2003-12-01), Langford, II
patent: 7266742 (2007-09-01), Pandey
patent: 7456674 (2008-11-01), Oakland
patent: 2007/0200597 (2007-08-01), Oakland
patent: 2008/0122515 (2008-05-01), Oakland
“Methods for improving transition delay fault coverage using broadside tests” by Devtaprasanna et al. This paper appears in: Test Conference, 2005. Proceedings. ITC 2005. IEEE International Publication Date: Nov. 8-8, 2005 On p. 10 pp. 265 ISBN: 0-7803-9038-5 INSPEC Accession No. 9004537.
“Novel Bi-partitioned Scan Architecture to Improve Transition Fault Coverage” by Devanathan, V.R. This paper appears in: Test Symposium, 2005. Proceedings. 14th Asian Publication Date: Dec. 18-21, 2005 On pp. 300-305 ISSN: 1081-7735 ISBN: 0-7695-2481-8.
Ahmed, Nisar , et al., “At-Speed Transition Fault Testing Using Low Speed Testers With Application to Reduced Scan Enable Routing Area”,IEEE North Atlantic Test Workshop(NATW'05), (2005), 8 pages.
Ahmed, Nisar , et al., “At-Speed Transition Fault Testing With Low Speed Scan Enable”,23rd IEEE VLSI Test Symposium(VTS'05), (2005), 7 pages.

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