At-speed built-in self testing of multi-port compact sRAMs

Details At-speed built-in self testing of multi-port compact sRAMs At-speed built-in self testing of multi-port compact sRAMs

1999-09-23

2003-01-21

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S042000, C714S718000

Reexamination Certificate

active

06510530

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is generally concerned with a method and apparatus for testing memories and in particular with a Built-In Self Test (BIST) for at-speed testing of multi-port compact static random access memories (CsRAMs).
2. Description of the Related Art
A RAM (random access memory) comprises a plurality of storage elements or cells, and a number of ports for each cell. Generally, a port includes five connections accessible to the external equipment, namely a data-in, a data-out, a clock, an address, and a control (write/read) connection. For a one-port memory, the cells are accessed sequentially, according to the address, and a data bit (0 or 1) is written or read in/from the respective cell.
New generation of ASICs for the telecommunications industry requires larger and faster memories. To deal with the increased demand of data processing, compact sRAMs (CsRAMs) were developed, which reduce the silicon area and the peak power consumption of conventional memories. Compact static RAMs are currently used in ASICs on a large scale, due to their higher yields, lower costs, and faster access time.
A CsRAM is a multi-port memory design methodology, where a set of read/write and address decoding circuitry is shared among multiple ports in a time slice fashion. In other words, in a single system clock cycle, each port is given a fraction of the cycle time to access the memory through the same read/write circuitry as well as the same address decoder. Compared to a conventional multi-port memory, a CsRAM that supports the same number of ports as a conventional one occupies significantly less silicon area.
Conventionally, testing of a memory device comprises writing a data pattern at a predetermined location, reading the data out from the respective location and comparing it with the data that should have been written into that location.
In the past, memory devices were tested at the manufacturing site using an external tester that supplied control signals, address signals, and data signals to the memory under test, and also did the evaluation of the output data in order to determine whether the memory passes or fails.
As the density of the memory cells on a single chip increases, so does the need to test the circuits after they are packaged in an ASIC. A fault, which is not detected during manufacturing test, will result in unexpected failures in the field. However, testing memory chips is not an easy task. For example, the number of connections with the outside equipment is limited. A straightforward implementation of multiple physical ports throughout the memory is prohibitively complex and unpractical.
Testing of embedded memory blocks in ASICs is very challenging. Firstly, high-speed memories use a small differential signal swing, so that special test algorithms must be used, making detection of shorts difficult. In addition, as the scale of the integrated circuits increases, so does the number and type of errors. As a result, the number of test patterns required for testing various types of defects, as well as the duration of execution of the pattern also grow with the memory size.
Furthermore, accessing the memory for writing and reading, then comparing the response is a major challenge when the array is buried deep down in the logic. As a result, the test patterns required for fault evaluation of high speed memories become more sophisticated, which in turn increases the test time and the size of chip. A general solution to this problem is to embed additional test circuits into the chip itself and to perform a built-in self test (BIST). Inclusion of a BIST in the ASIC is an elegant method to obtain very high fault coverage with minimum test time.
Current BIST controllers include a finite state machine (FSM) that provides for a specific sequence of write, read, and compare operations. The test may be conducted by the user whenever needed, or it can be automatically initiated at start up. As used throughout the disclosure, “BIST” refers to the actual test, while “BIST controller” refers to the circuitry that performs the BIST.
Methods for testing CsRAMs comprise a two part test, the first part being a scan test for the control logic of the CsRAM, and the second part being a conventional BIST for testing the memory itself. Although this method has a good coverage for static defects in both the control logic and the memory, it misses many timing-related defects in the memory.
To summarize, conventional memory test methodologies do not yield a satisfactory coverage when applied to CsRAMs. This is mostly due to the fact that CsRAMs run at their internal clock which is many times faster than the system clock. Currently, CsRAMs are tested at the much lower system clock speed and therefore, many timing-related defects are not uncovered.
It is a need for a practical method for testing CsRAMs at full memory speed in order to detect all timing-related defects in the memory.
SUMMARY OF THE INVENTION
It is an object of the present invention to alleviate totally or in part the above-mentioned drawbacks of the prior art BIST controllers.
Another object of this invention is to detect most or all timing-related defects in CsRAMs, using a standard Built-in Self-Test (BIST) controller. The method according to the invention requires a minimal addition of test circuitry around a conventional memory array and minimal changes to the conventional test algorithm. It is to be understood that the present invention can also be implemented as a one-piece, dedicated BIST controller.
According to one aspect of the invention, a method for testing a 2-port compact static random access memory (CsRAM) at the working speed of said CsRAM, is provided. The method comprises a first testing session and a second testing session. The first session includes generating a first set of test data and a second set of test data which may be identical or complementary to the first set, simultaneously writing the first set of test data in a first section of the CsRAM, and the second set of test data in a second section, reading a first output data from the first section and a second output data from the second section, and comparing the first output and the second output with the respective first and second set of test data and declaring a fault whenever the first output differs from the first test data, or the second output differs from the second test data.
The second session includes simultaneously writing the first set of test data in the second section of the CsRAM, and the second set of test data in the first section, reading the first output data from the second section and the second output data from the first section, and comparing again each output with respective first and second set of test data and declaring a fault whenever the first output differs from the first test data or the second output differs from the second test data. The method for testing a 2-port CsRAM can be applied to the testing of multi-port CsRAMs.
According to another aspect of the invention, a test circuit for a CsRAM with a first and a second port is provided. The circuit comprises a first address multiplexer unit for the first port and a second address multiplexer unit for the second port for selecting one of a test address and a system address in a first and respectively a second section of said CsRAM, a first data multiplexer unit for the first port and a second data multiplexer unit for the second port for providing one of a test data word and a system data word in the first and respectively the second section, a first W/R multiplexer unit for the first port and a second W/R multiplexer unit for the second port, said W/R multiplexer units for providing one of a test write/read instruction and a system write/read instruction for both the first and second sections, and a built-in self test (BIST) controller for generating test addresses, test data word and test write/read instruction simultaneously on the first and second ports, and for receiving an output data from said CsRAM, to pe

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