Electrical computers and digital processing systems: processing – Processing control – Specialized instruction processing in support of testing,...
Reexamination Certificate
2001-10-03
2003-07-22
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Processing control
Specialized instruction processing in support of testing,...
C714S731000, C714S729000
Reexamination Certificate
active
06598150
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems having a program counter register storing a program counter value pointing to an instruction being executed and having a mechanism for accessing that program counter value for diagnostic purposes.
2. Description of the Prior Art
When performing diagnostic operations, such as de-bugging, on a data processing system executing program instructions, it is often useful to know which instructions within the overall software code are being executed. One way of achieving this is to use data capturing hardware on the relevant buses within the data processing system to generate a trace output of every single instruction that is executed as a stream of real time data. A problem with this approach is that high speed and expensive memories are needed to store the very large quantities of data generated and the storage capacity of such memory means that only small intervals of time can be monitored completely.
Another approach is to perform code profiling in which the program counter value is sampled at known times and a statistical picture of the contents of the program counter register is gradually developed. One way of achieving such sampling is to apply an interrupt signal to the processing system to cause interrupt code to execute that outputs the value of the program counter register at the point that the interrupt occurred. A problem with this approach is that the interrupt necessarily disturbs the true behavior of the real time operation of the system and so in some circumstances can produce unrealistic results.
An alternative approach is software emulation of the processing system. Whilst such software emulation allows real time operation to be simulated in non-real time, it does have the problem that one can never be certain that a software emulation will truly represent the real behavior of the physical system. Software emulation is also disadvantageously slow.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising:
(i) a processor unit for executing data processing instructions;
(ii) a program counter register within said processor unit for storing an instruction address of a data processing instruction being executed by said processor unit;
(iii) a scan chain for serially transferring diagnostic data between said processor unit and a diagnostic system; and
(iv) a program counter latching circuit responsive to a program counter value request signal from said diagnostic system for latching an instruction address from said program counter register, transferring said instruction address to said scan chain and serially transferring said instruction address from said scan chain to said diagnostic system;
(v) wherein said scan chain and said program counter latching circuit operate independently of said processor unit such that execution of data processing instructions by said processor unit is unaltered by said action of said scan chain and said program counter latching logic.
The present invention recognizes that many modem data processing systems already incorporate scan chains that are used for other diagnostic purposes. These scan chains can be reused for accessing program counter values. Furthermore, rather than the data processing system itself continuously driving the high speed output of a large volume of program counter value data, the invention turns this arrangement around with the diagnostic system requesting the program counter values from the data processing system being analyzed. This arrangement greatly simplifies the handling of the diagnostic data making the program counter value information available at an advantageously reduced cost and complexity.
Whilst the program counter request signal could be an individually provided signal into the data processing system on a dedicated input, it is preferred that this should take the form of a diagnostic instruction serially transferred into the data processing system under test. In this way existing mechanisms for transferring diagnostic instructions can be added to so as to provide the function of the program counter request signal without incurring the cost of a dedicated signal pin or separate dedicated handling mechanisms.
It will be appreciated that the processor unit will typically be driven at a processor clock speed by a processor clock signal. In order to perform accurate diagnosis of real time operation, it is important that the processor unit should continue to be driven by this signal when the diagnostic operations are being performed. The diagnostic mechanisms within the system may often be unable to operate at the full processor clock speed and accordingly are driven by a separate scan chain clock signal that is independent of the processor clock signal. This prevents the diagnostic operations interfering with the processor unit, but does introduce a need for synchronization between the two clock signals such that a stable program counter value is sampled at an appropriate predetermined point within the processing clock cycle. Synchronizing hardware can be provided to achieve this.
A convenient way to embody the invention is to provide a program counter value shadowing register that continuously serves to store a shadow value of the program counter value current within the processor unit. This shadow value is continuously updated in synchronism with the real value and the shadow value is accessible for latching and output when instructed by the external diagnostic system.
In preferred embodiments the scan chains are part of a JTAG scan chain that may be controlled using readily available standard equipment and software.
The program counter latching circuit can conveniently be provided in combination with circuitry that monitors the address bus and data bus of the processor unit as these buses will bear signals that allow a program counter value to be determined and so be accessible for output to the diagnostic system. The program counter latching circuit may reuse logic that is already in place for other purposes, e.g. run control, coprocessor control, etc.
Whilst the invention could be used to recover program counter values for a variety of uses, it is particularly suited for use in code profiling where the true de-coupling of the processor unit operation and the diagnostic system ensures true operation of the processor unit and the statistical sampling of the program counter value provides a sufficient degree of information to draw useful code profiling conclusions.
The diagnostic system that issues the program counter request signals could be special purpose hardware produced for diagnostic purposes. However, the diagnostic system may conveniently be provided by a relatively low cost computer system operating under software control.
Whilst the invention is applicable for processing systems in general, it is particularly advantageous in the field of application specific integrated circuits where diagnostic information is highly useful in de-bugging the ASICs and yet access to the internal data, such as program counter values, can be difficult to achieve.
Viewed from another aspect the present invention provides a method of processing data, said method comprising the steps of:
(i) executing data processing instructions upon a processor unit;
(ii) storing in a program counter register within said processor unit an instruction address of a data processing instruction being executed by said processor unit;
(iii) in response to a program counter value request signal from a diagnostic system to a program counter latching circuit, latching an instruction address from said program counter register, transferring said instruction address to a scan chain and serially transferring said instruction address from said scan chain to said diagnostic system;
(iv) wherein said latching, said transferring and said serial transferring are performed independently of said pro
Merritt Andrew John
Williams Michael John
Arm Limited
Lin Wen-Tai
Maung Zarni
Nixon & Vanderhye P.C.
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