Static information storage and retrieval – Read/write circuit – Precharge
Patent
1989-06-23
1990-11-06
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Precharge
36523003, 3652335, G11C 1140
Patent
active
049691252
ABSTRACT:
An improved memory array having row address inputs connected to a row address decoder and column address inputs connected to a column address decoder, the row address decoder and column address decoder having an address bus connected thereto, the memory being organized into an array of word lines organized into rows and columns having a pair of bit lines for each column, the improvement comprising, segmenting the array into a plurality of segments, each segment containing a portion of all of the bit lines; a bit equalization circuit for each segment, to equalize the potential on each bit line in the bit line pair when activated; an equalization circuit control means, having an input coupled to the input address lines, and an output connected to each equalization circuit on each respective segment of the array, for enabling the equalization circuits on those segments of the array which are not selected by the input address and for disabling the equalization circuits on that segment of the array which is selected by the input address; the bit line pairs in the non-selected circuits being maintained in an equal potential state so that when one of the bit lines in a bit line pair in a non-selected segment suffers a discharge due to an ionizing radiation effect, the activated equalization circuit on the non-selected segment will equalize the potential thereof; whereby the radiation immunity of the memory array is improved. The resulting memory array has enhanced radiation hardness, reduced power dissipation, and is capable of static page mode operation.
REFERENCES:
patent: 4520465 (1985-05-01), Sood
patent: 4528646 (1985-07-01), Ochii et al.
patent: 4592026 (1986-05-01), Matsukawa et al.
patent: 4594689 (1986-06-01), Donoghue
patent: 4602354 (1986-07-01), Craycraft et al.
patent: 4612631 (1986-09-01), Ochii
patent: 4656610 (1987-04-01), Yoshida et al.
patent: 4710901 (1987-12-01), Kumanoya et al.
patent: 4730279 (1988-03-01), Ohtani
patent: 4742487 (1988-05-01), Bernstein
patent: 4780852 (1988-10-01), Kajigaya et al.
patent: 4839860 (1989-06-01), Shinoda et al.
Ciraula Michael K..
Durham Christopher Mc.
Harrison Reginald E.
Jallice Derwin J.
Lawson Dave C.
Hoel John E.
International Business Machines - Corporation
Popek Joseph A.
Wurm Mark A.
LandOfFree
Asynchronous segmented precharge architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous segmented precharge architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous segmented precharge architecture will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1311323