Asynchronous row and column control

Details Asynchronous row and column control Asynchronous row and column control

1985-08-05

1987-04-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365230, G11C 700

Patent

active

046619313

ABSTRACT:
A memory circuit has a plurality of bit line pairs and intersecting word lines with a memory cell located at each such intersection. A column address selects the bit line which is to be accessed and a row address selects the word line which is enabled. In response to being selected, a bit line is coupled to a data line. In response to a column address transition, all of the bit lines are decoupled from the data lines while bit lines are precharged. In response to a row address transition, the word lines are disabled while the bit lines are equilibrated.

REFERENCES:
patent: 4338679 (1982-07-01), O'Toole
patent: 4417328 (1983-11-01), Ochii
patent: 4581718 (1986-04-01), Oistic

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