Asynchronous memory using source synchronous transfer and...

Details Asynchronous memory using source synchronous transfer and... Asynchronous memory using source synchronous transfer and...

2006-06-06

2006-06-06

Padmanabhan, Mano (Department: 2188)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S105000, C711S154000, C365S193000, C365S194000

Reexamination Certificate

active

07058776

ABSTRACT:
A memory for storing data information and/or a controller for controlling read/write operations of the memory based on a source synchronous interface are provided. During the read/write operations, a command and an address are provided to the memory together with the first strobe signal. The memory may latch the command and address in response to the first strobe signal. During a read operation, the memory responds to a received second strobe signal to generate a third strobe signal. The memory outputs data from the memory and the third strobe signal, for example, so that the output data may be latched with the third strobe signal by the memory controller.

REFERENCES:
patent: 6047361 (2000-04-01), Ingenio et al.
patent: 6067632 (2000-05-01), Yamaguchi
patent: 6209071 (2001-03-01), Barth et al.
patent: 6311285 (2001-10-01), Rodriguez et al.
patent: 6336159 (2002-01-01), MacWilliams et al.
patent: 6477110 (2002-11-01), Yoo et al.

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