Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2000-12-27
2001-10-09
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S204000, C365S207000, C365S190000, C365S202000
Reexamination Certificate
active
06301176
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to asynchronous memory devices generally and, more particularly, to a method and/or architecture for implementing scaled timing associated with a dummy sense amplifier and dummy bit lines that determine when read data is valid.
BACKGROUND OF THE INVENTION
Asynchronous memories use a pair of bit lines to carry data from a bit cell of a selected column and a selected word to a sense amplifier. The bit lines are constantly pulled up by a pair of pullups and are sometimes tied together with an equalization circuit that is always operating. During a memory sense period of a read access operation, the bit cells override the pullups and equalization to cause one bit line to discharge below the other bit line. The sense amplifier presents a data value for the bit cell when the sense amplifier detects a predetermined voltage separation between the two bit lines. The predetermined voltage separation is around 10 percent of the supply voltage. The voltage separation remains on the bit lines until a word line is deasserted. Once the word line is deasserted, then the pullups bias the bit lines back to a precharged voltage.
A set of dummy bit lines, a dummy bit cell having a fixed data value, and a dummy sense amplifier are used to determine when the other sense amplifiers have had sufficient time to present valid data. The fixed data value of the dummy bit cell is selected such that the data presented by the dummy sense amplifier is a sense enable signal for the other sense amplifiers at the end of the read access operation. When the fixed data value is detected by the dummy sense amplifier, then the sense enable signal is deasserted causing data presented by the other sense amplifiers to freeze. Hereafter, the word lines are deasserted and the pullups and equalization circuits equalize all of the bit lines.
A problem with existing asynchronous memory designs is that the timing performed by the dummy bit lines, the dummy bit cell, and the dummy sense amplifier assumes that all other bit lines are starting from a predetermined initial voltage. The memory sense period of a subsequent read access operation cannot be started until the pullups and equalization circuits charge all of the bit lines to the predetermined initial voltage. A secondary precharge network could be used to shorten the time required to equalize the bit lines. Secondary precharge networks, however, require more space and can result in additional power consumption.
SUMMARY OF THE INVENTION
The present invention concerns a circuit that may be used in asynchronous memories. The circuit generally comprises a bit line, a complementary bit line, a memory cell, and a read circuit. The memory cell may be configured to (i) discharge the bit line in response to a memory sense period and (ii) charge the complementary bit line in response to said memory sense period. The read circuit may be configured to (i) precharge the bit line prior to the memory sense period, (ii) discharge the complementary bit line prior to the memory sense period, and (iii) detect when the bit line and the complementary bit line achieve a predetermined voltage separation in response to the memory sense period.
The objects, features and advantages of the present invention include providing a method and/or architecture for (i) an easily scaled compensation to timing associated with a dummy sense amplifier and a dummy bit line pair to account for other bit line pairs having to transition from a maximum opposite separation as a starting point in asynchronous memories, and/or (ii) reduce or eliminate a need to equilibrate the other bit line pairs prior to each read access operation.
REFERENCES:
patent: 6108255 (2000-08-01), Ciraula et al.
Lam David
LSI Logic Corporation
Nelms David
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