Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2006-09-12
2006-09-12
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
Signals
C365S233500, C365S233100, C365S230080, C365S222000
Reexamination Certificate
active
07106637
ABSTRACT:
An asynchronous address interface circuit and method for converting unrestricted randomly scheduled address transitions of memory address signals into scheduled address events from which initiation of a sequence of memory access events can be based. The address interface circuit initiates a delay sequence based on a address transition detection pulse. In the event a new address transition detection pulse is received prior to completion of the delay sequence, the delay sequence is reset and restarted based on the new address transition detection pulse. The sequence of memory access events is initiated in response to the completion of the delay sequence.
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Lovett Simon J.
Norwood Roger D.
Schreck John F.
Shirley Brian M.
Zitlaw Cliff
Dorsey & Whitney LLP
Le Toan
Micro)n Technology, Inc.
Phung Anh
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