Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Signal level or switching threshold stabilization
Reexamination Certificate
2007-12-28
2010-10-26
Cho, James (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Signal level or switching threshold stabilization
C326S033000
Reexamination Certificate
active
07821293
ABSTRACT:
An embodiment of the present invention relates to a asynchronous interconnection system comprising a transmitter circuit and a receiver circuit inserted between inserted between respective first and second voltage references and having respective transmitter and receiver nodes coupled in a capacitive manner. The receiver circuit comprises: a recovery stage inserted between the first and second voltage references of the receiver circuit and connected to the receiver node; and a state control stage, in turn inserted between the first and second voltage references of the receiver circuit connected to the recovery stage correspondence with a first feedback node providing a first control signal and having a second feedback node connected in a feedback manner to the recovery stage. The recovery stage comprises a first feedback loop connected to the first feedback node and acting in such a way to recover a received voltage signal and a feedback loop connected to the second feedback node of the state control stage and acting in such a way to deactivate the recovery feedback on the receiver node and guarantee that the receiver node is let in a high impedance state.
REFERENCES:
patent: 4723082 (1988-02-01), Asano et al.
patent: 5220205 (1993-06-01), Shigehara et al.
patent: 5629838 (1997-05-01), Knight et al.
patent: 5760618 (1998-06-01), Deliyannides et al.
patent: 6016064 (2000-01-01), Saeki
patent: 6600325 (2003-07-01), Coates et al.
Kaustav Banerjee, Shukri J. Souri, Pawan Kapur, and Krishna C. Saraswat, “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration”, Proceedings of the IEEE, May 2001, pp. 602-633, vol. 89, No. 5.
Kouichi Kanda, Danardono Dwi Antono, Koichi Ishida, Hiroshi Kawaguchi, Tadahiro Kuroda', and Takayasu Sakurai, “1.27Gb/s/pin 3mW/pin Wireless Superconnect (WSC) Interface Scheme”, ISSCC Dig. Tech. Papers, Feb. 2003, pp. 186-187.
Robert J. Drost, Robert David Hopkins, Ron Ho, and Ivan E. Sutherland, “Proximity Communication”, IEEE Journal of Solid-State Circuits, Sep. 2004, pp. 1529-1535, vol. 39, No. 9.
Stephen Mick, John Wilson and Paul Franzon, “4 Gbps High-Density AC Coupled Interconnection”, CICC2002, IEEE 2002 Custom Integrated Circuits Conference, pp. 133-140.
Lei Luo, John M. Wilson, Stephen E. Mick, Jian Xu, Liang Zhang, and Paul D. Franzon, “3Gb/s AC-Coupled Chip-to-Chip Communication using a Low-Swing Pulse Receiver”, ISSCC2005, pp. 522, 523, 614.
Canegallo Roberto
Ciccarelli Luca
Fazzi Alberto
Guerrieri Roberto
Magagni Luca
Cho James
Graybeal Jackson LLP
Jablonski Kevin D.
Jorgenson Lisa K.
STMicroelectronics S.r.l.
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