Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2005-12-20
2005-12-20
Perveen, Rehana (Department: 2112)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C710S107000
Reexamination Certificate
active
06978391
ABSTRACT:
In microcomputers for being embedded into various devices, asynchronous bus interface circuits are arranged between an asynchronous bus and macro circuits, operating in synchronization with an operational clock. Each asynchronous bus interface circuit includes an external register, a synchronizing buffer, an arbitration circuit and an internal register. The external register stores data in response to a write-request signal from the bus. The synchronizing buffer receives this data from the external register and outputs the data in synchronization with the clock. The arbitration circuit outputs an internal register-write signal in synchronization with the clock, in response to the write-request signal. The internal register receives the data from the synchronizing buffer upon reception of the internal-register-write signal, and outputs the received data to the macro circuit in synchronization with the clock. Upon reception of the following write-request signal, the arbitration circuit suppresses the internal register-write signal corresponding to the preceding write-request signal.
REFERENCES:
patent: 5047921 (1991-09-01), Kinter et al.
patent: 5598542 (1997-01-01), Leung
patent: 5949789 (1999-09-01), Davis et al.
patent: 6249847 (2001-06-01), Chin et al.
patent: 49-53342 (1974-05-01), None
patent: 57-59243 (1982-04-01), None
patent: 57-182838 (1982-11-01), None
patent: 57-191749 (1982-11-01), None
patent: 60-160461 (1985-08-01), None
patent: 61-180357 (1986-08-01), None
patent: 64-9563 (1989-01-01), None
patent: 03-132857 (1991-06-01), None
patent: 05-197676 (1993-08-01), None
patent: 06-83768 (1994-03-01), None
patent: 11-73389 (1999-03-01), None
Japanese Office Action dated Feb. 12, 2003, with partial English translation.
Ito Ken-ichi
Kobayashi Ryousaku
Knoll Clifford
McGinn IP Law Group, PLLC.
NEC Electronics Corporation
Perveen Rehana
LandOfFree
Asynchronous bus interface circuit, method of controlling... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Asynchronous bus interface circuit, method of controlling..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Asynchronous bus interface circuit, method of controlling... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3488489