Asymmetrical vertical lightly doped drain transistor and method

Details Asymmetrical vertical lightly doped drain transistor and method Asymmetrical vertical lightly doped drain transistor and method

1996-10-17

1998-11-10

Monin, Donald

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257408, 257623, H01L 21336

Patent

active

058348107

ABSTRACT:
An asymmetrical vertical lightly doped drain metal oxide semiconductor field effect transistor (VLDD MOSFET) is formed on a semiconductor substrate. The substrate includes first and second main planar surfaces with the second main planar surface parallel to and positioned at a height lower that the first main planar surface. A third planar surface, generally normal to the first and second main planar surfaces, connects the first and second main planar surfaces on the drain region side of the channel region. The source region is formed in a portion of the first main planar surface, and the drain region is formed in the third planar surfaces and portions of the first and second main planar surfaces. Contours of equal ion concentration in the drain region are non-Gaussian and an interface between the channel region and drain region is generally linear beneath the gate electrode adjacent the generally normal third planar surface.

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